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* Merge tag 'kernel-hardening-v5.19-rc1' of git://git.kernel.org/pub/scm/linux/...Linus Torvalds2022-05-244-24/+7
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| * arm64: entry: use stackleak_erase_on_task_stack()Mark Rutland2022-05-081-1/+1
| * arm64: stackleak: fix current_top_of_stack()Mark Rutland2022-05-081-6/+4
| * randstruct: Split randstruct Makefile and CFLAGSKees Cook2022-05-081-1/+2
| * cfi: Use __builtin_function_startSami Tolvanen2022-04-131-16/+0
* | Merge tag 'perf-core-2022-05-23' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds2022-05-242-0/+2
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| * \ Merge branch 'v5.18-rc5'Peter Zijlstra2022-05-1141-232/+276
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| * | | signal: Deliver SIGTRAP on perf event asynchronously if blockedMarco Elver2022-04-222-0/+2
* | | | Merge tag 'locking-core-2022-05-23' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds2022-05-241-4/+4
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| * | | | lockdep: Fix -Wunused-parameter for _THIS_IP_Nick Desaulniers2022-04-051-4/+4
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* | | | Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds2022-05-2380-657/+3174
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| * \ \ \ Merge branch 'for-next/esr-elx-64-bit' into for-next/coreCatalin Marinas2022-05-2026-140/+145
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| | * | | | KVM: arm64: uapi: Add kvm_debug_exit_arch.hsr_highAlexandru Elisei2022-04-293-0/+5
| | * | | | KVM: arm64: Treat ESR_EL2 as a 64-bit registerAlexandru Elisei2022-04-299-20/+20
| | * | | | arm64: Treat ESR_ELx as a 64-bit registerAlexandru Elisei2022-04-2914-116/+116
| | * | | | arm64: compat: Do not treat syscall number as ESR_ELx for a bad syscallAlexandru Elisei2022-04-291-1/+1
| | * | | | arm64: Make ESR_ELx_xVC_IMM_MASK compatible with assemblyAlexandru Elisei2022-04-291-1/+1
| * | | | | Merge branch 'for-next/sysreg-gen' into for-next/coreCatalin Marinas2022-05-2019-220/+784
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| | * | | | | arm64/sysreg: Generate definitions for FAR_ELxMark Brown2022-05-202-3/+12
| | * | | | | arm64/sysreg: Generate definitions for DACR32_EL2Mark Brown2022-05-202-1/+20
| | * | | | | arm64/sysreg: Generate definitions for CSSELR_EL1Mark Brown2022-05-202-2/+7
| | * | | | | arm64/sysreg: Generate definitions for CPACR_ELxMark Brown2022-05-202-2/+20
| | * | | | | arm64/sysreg: Generate definitions for CONTEXTIDR_ELxMark Brown2022-05-202-2/+17
| | * | | | | arm64/sysreg: Generate definitions for CLIDR_EL1Mark Brown2022-05-202-1/+16
| | * | | | | arm64/sve: Generate ZCR definitionsMark Brown2022-05-162-7/+18
| | * | | | | arm64/sme: Generate defintions for SVCRMark Brown2022-05-162-4/+6
| | * | | | | arm64/sme: Generate SMPRI_EL1 definitionsMark Brown2022-05-162-3/+5
| | * | | | | arm64/sme: Automatically generate SMPRIMAP_EL2 definitionsMark Brown2022-05-162-1/+19
| | * | | | | arm64/sme: Automatically generate SMIDR_EL1 definesMark Brown2022-05-162-1/+9
| | * | | | | arm64/sme: Automatically generate defines for SMCRMark Brown2022-05-162-10/+20
| | * | | | | arm64/sysreg: Support generation of RAZ fieldsMark Brown2022-05-161-0/+7
| | * | | | | arm64/sme: Remove _EL0 from name of SVCR - FIXME sysreg.hMark Brown2022-05-169-35/+35
| | * | | | | arm64/sme: Standardise bitfield names for SVCRMark Brown2022-05-164-8/+8
| | * | | | | arm64/sme: Drop SYS_ from SMIDR_EL1 definesMark Brown2022-05-162-4/+4
| | * | | | | arm64/fp: Rename SVE and SME LEN field name to _WIDTHMark Brown2022-05-162-4/+4
| | * | | | | arm64/fp: Make SVE and SME length register definition match architectureMark Brown2022-05-161-14/+4
| | * | | | | Merge branch 'for-next/sme' into for-next/sysreg-genCatalin Marinas2022-05-1632-130/+1955
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| | * | | | | | arm64/sysreg: fix odd line spacingMark Rutland2022-05-151-3/+3
| | * | | | | | arm64/sysreg: improve comment for regs without fieldsMark Rutland2022-05-151-1/+1
| | * | | | | | arm64/sysreg: Generate definitions for SCTLR_EL1Mark Brown2022-05-042-38/+71
| | * | | | | | arm64/sysreg: Generate definitions for TTBRn_EL1Mark Brown2022-05-042-2/+14
| | * | | | | | arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1Mark Brown2022-05-042-20/+67
| | * | | | | | arm64/sysreg: Enable automatic generation of system register definitionsMark Brown2022-05-043-1/+16
| | * | | | | | arm64: Add sysreg header generation scriptingMark Rutland2022-05-042-0/+309
| | * | | | | | arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro namesMark Brown2022-05-044-67/+67
| | * | | | | | arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARMMark Brown2022-05-043-5/+5
| | * | | | | | arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1Mark Brown2022-05-041-21/+32
| | * | | | | | arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWIMark Brown2022-05-041-3/+3
| | * | | | | | arm64/mte: Make TCF field values and naming more standardMark Brown2022-05-043-12/+14
| | * | | | | | arm64/mte: Make TCF0 naming and field values more standardMark Brown2022-05-042-7/+7
generated by cgit (git 2.34.1) at 2025-02-25 17:10:12 +0000