linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	RISC-V: Probe Svinval extension form ISA string	Mayuresh Chitale	2022-10-02	1	-0/+4
*	RISC-V: Add Sstc extension support	Palmer Dabbelt	2022-08-11	1	-0/+1
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\| *	RISC-V: Enable sstc extension parsing from DT	Atish Patra	2022-08-11	1	-0/+1
* \|	arch/riscv: add Zihintpause support	Dao Lu	2022-08-11	1	-0/+5
* \|	riscv: Add support for non-coherent devices using zicbom extension	Heiko Stuebner	2022-07-28	1	-0/+1
* \|	riscv: introduce unified static key mechanism for ISA extensions	Jisheng Zhang	2022-06-16	1	-0/+25
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*	riscv: add RISC-V Svpbmt extension support	Heiko Stuebner	2022-05-11	1	-0/+1
*	RISC-V: Add sscofpmf extension support	Atish Patra	2022-03-21	1	-0/+1
*	RISC-V: Improve /proc/cpuinfo output for ISA extensions	Atish Patra	2022-03-17	1	-0/+7
*	RISC-V: Implement multi-letter ISA extension probing framework	Atish Patra	2022-03-17	1	-0/+18
*	RISC-V: Add bitmap reprensenting ISA features common across CPUs	Anup Patel	2020-05-04	1	-0/+22
*	riscv: clean up the macro format in each header file	Zong Li	2019-11-12	1	-3/+4
*	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 234	Thomas Gleixner	2019-06-19	1	-12/+1
*	RISC-V: ELF and module implementation	Palmer Dabbelt	2017-09-26	1	-0/+37