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path: root/drivers/cxl/core
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* cxl/region: Recycle region idsDan Williams2022-11-041-0/+20
* cxl/region: Fix 'distance' calculation with passthrough portsDan Williams2022-11-042-3/+17
* cxl/pmem: Fix cxl_pmem_region and cxl_memdev leakDan Williams2022-11-041-0/+2
* cxl/region: Fix cxl_region leak, cleanup targets at region deleteDan Williams2022-11-041-0/+11
* cxl/region: Fix region HPA ordering validationDan Williams2022-11-041-0/+3
* cxl/region: Fix decoder allocation crashVishal Verma2022-11-011-26/+41
* cxl/region: Fix null pointer dereference due to pass through decoder commitJonathan Cameron2022-10-201-1/+2
* cxl/mbox: Add a check on input payload sizeJonathan Cameron2022-10-201-1/+1
* cxl/hdm: Fix skip allocations vs multiple pmem allocationsDan Williams2022-08-051-1/+10
* cxl/region: Disallow region granularity != window granularityDan Williams2022-08-051-6/+7
* cxl/region: Fix x1 interleave to greater than x1 interleave routingDan Williams2022-08-051-1/+5
* cxl/region: Move HPA setup to cxl_region_attach()Dan Williams2022-08-052-26/+24
* cxl/region: Fix decoder interleave programmingDan Williams2022-08-051-0/+3
* cxl/regions: add padding for cxl_rr_ep_add nested listsBagas Sanjaya2022-08-051-0/+3
* cxl/region: Fix region reference target accountingDan Williams2022-08-051-28/+43
* cxl/region: Fix region commit uninitialized variable warningDan Williams2022-08-051-17/+13
* cxl/region: Fix port setup uninitialized variable warningsDan Williams2022-08-051-3/+22
* cxl/region: Stop initializing interleave granularityDan Williams2022-08-011-4/+0
* cxl/hdm: Fix DPA reservation vs cxl_endpoint_decoder lifetimeDan Williams2022-08-011-2/+5
* cxl/region: Delete 'region' attribute from root decodersDan Williams2022-08-011-1/+2
* cxl/region: decrement ->nr_targets on error in cxl_region_attach()Dan Carpenter2022-08-011-1/+3
* cxl/region: prevent underflow in ways_to_cxl()Dan Carpenter2022-08-011-2/+3
* cxl/region: uninitialized variable in alloc_hpa()Dan Carpenter2022-08-011-1/+1
* cxl/region: Introduce cxl_pmem_region objectsDan Williams2022-07-264-3/+148
* cxl/region: Add region driver boiler plateDan Williams2022-07-263-1/+65
* cxl/hdm: Commit decoder state to hardwareDan Williams2022-07-253-10/+412
* cxl/region: Program target listsDan Williams2022-07-253-11/+257
* cxl/region: Attach endpoint decodersDan Williams2022-07-253-12/+369
* cxl/acpi: Add a host-bridge index lookup mechanismDan Williams2022-07-251-0/+16
* cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams2022-07-254-2/+310
* cxl/region: Allocate HPA capacity to regionsDan Williams2022-07-251-1/+149
* cxl/region: Add interleave geometry attributesBen Widawsky2022-07-251-0/+134
* cxl/region: Add a 'uuid' attributeBen Widawsky2022-07-251-0/+118
* cxl/region: Add region creation supportBen Widawsky2022-07-214-0/+251
* cxl/mem: Enumerate port targets before adding endpointsDan Williams2022-07-211-0/+41
* cxl/hdm: Add sysfs attributes for interleave ways + granularityBen Widawsky2022-07-211-0/+23
* cxl/port: Move dport tracking to an xarrayDan Williams2022-07-212-51/+40
* cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams2022-07-211-31/+29
* cxl/port: Record parent dport when adding portsDan Williams2022-07-211-12/+15
* cxl/port: Record dport in endpoint referencesDan Williams2022-07-211-17/+35
* cxl/hdm: Add support for allocating DPA to an endpoint decoderDan Williams2022-07-213-1/+259
* cxl/hdm: Track next decoder to allocateDan Williams2022-07-212-0/+16
* cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams2022-07-212-0/+30
* cxl/hdm: Enumerate allocated DPADan Williams2022-07-211-11/+134
* cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams2022-07-212-13/+27
* cxl/core: Define a 'struct cxl_root_decoder'Dan Williams2022-07-211-7/+27
* cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams2022-07-212-75/+150
* cxl/port: Read CDAT tableIra Weiny2022-07-191-0/+173
* cxl/hdm: Initialize decoder type for memory expander devicesDan Williams2022-07-101-5/+11
* cxl/port: Cache CXL host bridge dataDan Williams2022-07-101-1/+17
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