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path: root/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
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* drm/amdgpu: extend halt_if_hws_hang to MESGraham Sider2022-11-041-0/+4
* drm/amdgpu: remove deprecated MES version varsGraham Sider2022-10-271-4/+0
* drm/amdgpu: move mes self test after drm sched re-startedJack Xiao2022-07-281-1/+2
* drm/amdgpu/mes: init aggregated doorbellLe Ma2022-07-131-1/+57
* drm/amdgpu/mes: set correct mes ring ready flagJack Xiao2022-07-121-0/+3
* drm/amdgpu/mes: fix mes submission in atomic contextJack Xiao2022-07-081-32/+23
* drm/amdgpu/gfx10: enable kiq to map mes ringJack Xiao2022-05-041-66/+40
* drm/amdgpu: add mes unmap legacy queue routineJack Xiao2022-05-041-3/+66
* drm/amdgpu/mes10.1: add mes self test in late initJack Xiao2022-05-041-0/+10
* drm/amdgpu/mes10.1: implement the suspend/resume routineJack Xiao2022-05-041-2/+16
* drm/amdgpu/mes10.1: add delay after mes engine enableJack Xiao2022-05-041-0/+1
* drm/amdgpu/mes10.1: call general mes initializationJack Xiao2022-05-041-0/+5
* drm/amdgpu/mes: relocate status_fence slot allocationJack Xiao2022-05-041-33/+0
* drm/amdgpu: enable mes kiq N-1 test on sienna cichlidJack Xiao2022-05-041-38/+164
* drm/amdgpu/mes: extend mes framework to support multiple mes pipesJack Xiao2022-05-041-87/+128
* drm/amdgpu: use ring structure to access rptr/wptr v2Jack Xiao2022-05-041-6/+5
* drm/amdgpu: add the sched_score to amdgpu_ring_initChristian König2021-04-091-1/+2
* drm/ttm: cleanup BO size handling v3Christian König2020-12-141-1/+1
* drm/amdgpu: use "*" adjacent to data nameDeepak R Varma2020-11-021-1/+1
* drm/amdgpu/mes: simplify the return expression of mes_v10_1_ring_initQinglang Miao2020-09-221-6/+1
* drm/amdgpu/mes10.1: add no scheduler flag for mesAlex Deucher2020-07-011-0/+1
* drm/amdgpu/mes: allocate memory slots for hw resource settingLe Ma2020-07-011-0/+36
* drm/amdgpu/mes: add status fence memory definitionsLe Ma2020-07-011-0/+2
* drm/amdgpu/mes: correct register offset for sienna_cichlidLikun Gao2020-07-011-4/+35
* drm/amdgpu/mes10.1: update mes initializationJack Xiao2020-07-011-5/+15
* drm/amdgpu/mes10.1: copy mes fw info into global fw arrayJack Xiao2020-07-011-0/+17
* drm/amdgpu/mes10.1: add sienna_cichlid mes firmware supportJack Xiao2020-07-011-0/+4
* drm/amdgpu/mes10.1: implement setting hardware resourcesJack Xiao2020-07-011-0/+41
* drm/amdgpu/mes10.1: implement querying the scheduler statusJack Xiao2020-07-011-0/+19
* drm/amdgpu/mes10.1: implement removing hardware queueJack Xiao2020-07-011-1/+18
* drm/amdgpu/mes10.1: implement adding hardware queueJack Xiao2020-07-011-1/+49
* drm/amdgpu/mes10.1: add the helper function for mes command submissionJack Xiao2020-07-011-0/+30
* drm/amdgpu/mes10.1: add the mes fw apiJack Xiao2020-07-011-0/+1
* drm/amdgpu/mes10.1: enable the mes ring during initializationJack Xiao2020-07-011-0/+31
* drm/amdgpu/mes10.1: install mes queue via kiqJack Xiao2020-07-011-0/+27
* drm/amdgpu/mes10.1: install mes queue by register programmingJack Xiao2020-07-011-0/+62
* drm/amdgpu/mes10.1: initialize the mqdJack Xiao2020-07-011-0/+130
* drm/amdgpu/mes10.1: allocate mqd bufferJack Xiao2020-07-011-0/+37
* drm/amdgpu/mes10.1: implement the ring functions of mes specificJack Xiao2020-07-011-0/+43
* drm/amdgpu/mes10.1: initialize the software part of mes ringJack Xiao2020-07-011-0/+26
* drm/amdgpu/mes10.1: allocate the eop bufferJack Xiao2020-07-011-0/+33
* Merge branch 'drm-next' into drm-next-5.3Alex Deucher2019-06-251-0/+1
* drm/amdgpu/mes10.1: enable mes FW backdoor loadingJack Xiao2019-06-211-0/+36
* drm/amdgpu/mes10.1: implement mes enablement functionJack Xiao2019-06-211-0/+33
* drm/amdgpu/mes10.1: implement MES firmware backdoor loadingJack Xiao2019-06-211-0/+67
* drm/amdgpu/mes10.1: implement ucode buffers destructionJack Xiao2019-06-211-0/+11
* drm/amdgpu/mes10.1: upload mes data ucode to gpu bufferJack Xiao2019-06-211-0/+32
* drm/amdgpu/mes10.1: upload mes ucode to gpu bufferJack Xiao2019-06-211-0/+34
* drm/amdgpu/mes10.1: implement ucode CPU buffer destructionJack Xiao2019-06-211-0/+6
* drm/amdgpu/mes10.1: load mes firmware file to CPU bufferJack Xiao2019-06-211-0/+43
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