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path: root/drivers/gpu/drm/i915/display/intel_ddi.c
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* drm/i915/tgl+: Add locking around DKL PHY register accessesImre Deak2022-10-311-40/+28
* drm/i915: Force DPLL calculation for TC ports after readoutVille Syrjälä2022-09-271-3/+15
* drm/i915: Relocate intel_crtc_dotclock()Ville Syrjälä2022-09-071-22/+0
* drm/i915/quirks: abstract checking for display quirksJani Nikula2022-08-311-1/+2
* drm/i915: move hotplug to display.hotplugJani Nikula2022-08-291-3/+3
* drm/i915: move dpll under display.dpllJani Nikula2022-08-291-12/+12
* drm/i915/tc: Fix PHY ownership programming in HDMI legacy modeImre Deak2022-08-151-2/+8
* Merge drm/drm-next into drm-intel-nextRodrigo Vivi2022-08-041-1/+1
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| * Merge tag 'drm-intel-next-2022-07-06' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2022-07-121-1/+1
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| * \ Merge tag 'drm-intel-next-2022-06-22' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2022-06-241-31/+21
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| * \ \ Merge tag 'drm-intel-next-2022-05-06' of git://anongit.freedesktop.org/drm/dr...Dave Airlie2022-05-111-3/+3
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| * | | | drm/display: Move SCDC helpers into display-helper libraryThomas Zimmermann2022-04-251-1/+1
* | | | | drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling orderImre Deak2022-07-181-1/+5
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* | | | drm/i915: Nuke PCH_MCCVille Syrjälä2022-07-061-1/+1
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* | | drm/i915: Extract intel_crtc_dotclock()Ville Syrjälä2022-06-141-6/+12
* | | drm/i915/regs: split out intel audio register definitionsJani Nikula2022-06-031-0/+1
* | | drm/i915/display: stop using BUG()Jani Nikula2022-06-011-5/+6
* | | drm/i915: Extract intel_edp_fixup_vbt_bpp()Ville Syrjälä2022-05-271-20/+2
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* | drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platformImre Deak2022-04-201-3/+3
* | drm/i915: Rename the power domain names to end with pipes/portsImre Deak2022-04-201-1/+1
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* drm/i915/dg2: Do not explode on phy calibration errorLucas De Marchi2022-04-111-2/+1
* drm/i915/audio: move has_audio checks to within codec enable/disableJani Nikula2022-03-301-10/+4
* drm/i915: Do DRRS disable/enable during pre/post_plane_update()Ville Syrjälä2022-03-161-4/+0
* drm/i915: Move DRRS enable/disable higher upVille Syrjälä2022-03-151-3/+0
* drm/i915: Stash DRRS state under intel_crtcVille Syrjälä2022-03-151-1/+3
* drm/i915: Eliminate the intel_dp dependency from DRRSVille Syrjälä2022-03-151-5/+3
* drm/i915: Use str_enable_disable()Lucas De Marchi2022-03-021-1/+3
* drm/i915/dg2: Skip output init on PHY calibration failureMatt Roper2022-02-241-0/+8
* drm/i915/adlp: Add TypeC PHY TBT->DP-alt/legacy mode switch workaroundImre Deak2022-02-211-1/+18
* drm/i915: Change bigjoiner state tracking to use the pipe bitmaskVille Syrjälä2022-02-151-5/+7
* drm/i915: Introduce intel_crtc_is_bigjoiner_{slave,master}()Ville Syrjälä2022-02-151-1/+1
* drm/i915: Move M/N setup to a more logical place on ddi platformsVille Syrjälä2022-02-011-9/+1
* drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n()Ville Syrjälä2022-02-011-2/+4
* drm/i915: Split intel_cpu_transcoder_get_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä2022-02-011-6/+6
* drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variantsVille Syrjälä2022-02-011-3/+4
* drm/i915: Nuke intel_dp_get_m_n()Ville Syrjälä2022-02-011-2/+7
* drm/i915: Nuke intel_dp_set_m_n()Ville Syrjälä2022-02-011-1/+3
* drm/i915: s/gmch_{m,n}/data_{m,n}/Ville Syrjälä2022-01-281-2/+2
* drm/i915: Move dsc/joiner enable into hsw_crtc_enable()Ville Syrjälä2022-01-261-6/+0
* drm/i915: Nuke dg2_ddi_pre_enable_dp()Ville Syrjälä2022-01-241-113/+4
* drm/i915/display/adlp: Implement new step in the TC voltage swing prog sequenceJosé Roberto de Souza2022-01-131-0/+22
* drm/i915: Move TC PHY registers to their own headerMatt Roper2022-01-111-0/+1
* drm/i915: Move combo PHY registers to their own headerMatt Roper2022-01-111-0/+1
* drm/i915: Add privacy-screen support (v3)Hans de Goede2021-12-091-0/+16
* drm/i915: Call intel_update_active_dpll() for both bigjoiner pipesVille Syrjälä2021-11-101-1/+7
* drm/i915: Use intel_de_rmw() for icl combo phy programmingVille Syrjälä2021-11-031-26/+18
* drm/i915: Use intel_de_rmw() for icl mg phy programmingVille Syrjälä2021-11-031-73/+42
* drm/i915: Use intel_de_rmw() for tgl dkl phy programmingVille Syrjälä2021-11-031-21/+17
* drm/i915: Query the vswing levels per-lane for tgl dkl phyVille Syrjälä2021-11-031-14/+19
* drm/i915: Query the vswing levels per-lane for icl mg phyVille Syrjälä2021-11-031-1/+12
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