summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorCeping Sun <cepingx.sun@intel.com>2024-12-12 20:09:48 -0500
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2024-12-13 13:29:27 +0000
commitc1eb477e0629e3a444cab43c66a02fb8daf12ce9 (patch)
tree496f8db009758d111608bfd0c2971d1c65f953df
parent3022bab164cb761f24f8135ef3002e77df0bcd94 (diff)
downloadedk2-c1eb477e0629e3a444cab43c66a02fb8daf12ce9.tar.gz
OvmfPkg/TdxDxe: Clear GPR Mask for RBX
Refer to intel-tdx-module-api spec section 5.5.21, GPR mask (TDVMCALL_EXPOSE_REGS_MASK) is a bitmap that controls which part of the guest TD GPR and XMM state is passed as-is to the VMM and back. - A bit value of 0 indicates that the corresponding register is saved by the Intel TDX module and not passed as-is to Host VMM. - A bit value of 1 indicates that the corresponding register is passed as-is to the host VMM. Currently, RBX is used as the mailbox address in ApRunLoop.nasm, the corresponding bit value of RBX in MASK(Bit 3) is set as 1 which means the value is passed to Host VMM as-is and it can be changed by Host VMM. So the bitmask shall be set as 0 to avoid this situation. Reference: [TDX-API]: intel-tdx-module-abi-spec https://cdrdv2.intel.com/v1/dl/getContent/733579 Cc: Erdem Aktas <erdemaktas@google.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Hunter Adrian <adrian.hunter@intel.com> Signed-off-by: Ceping Sun <cepingx.sun@intel.com>
-rw-r--r--OvmfPkg/TdxDxe/X64/ApRunLoop.nasm2
1 files changed, 1 insertions, 1 deletions
diff --git a/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm b/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm
index 57560015f4..538ae71831 100644
--- a/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm
+++ b/OvmfPkg/TdxDxe/X64/ApRunLoop.nasm
@@ -20,7 +20,7 @@ SECTION .text
BITS 64
-%define TDVMCALL_EXPOSE_REGS_MASK 0xffcc
+%define TDVMCALL_EXPOSE_REGS_MASK 0xffc4
%define TDVMCALL 0x0
%define EXIT_REASON_CPUID 0xa