diff options
| author | Laszlo Ersek <lersek@redhat.com> | 2018-02-01 23:40:29 +0100 |
|---|---|---|
| committer | Laszlo Ersek <lersek@redhat.com> | 2018-04-04 16:44:06 +0200 |
| commit | c455687fd0babe03a203b38c9a884c65198d8c1d (patch) | |
| tree | cfaf6d86fd83174f8851813ad787ccb41fcbfa5f | |
| parent | fc504fdea7fe92bfa88e15f50e64b4d76d4f75fd (diff) | |
| download | edk2-c455687fd0babe03a203b38c9a884c65198d8c1d.tar.gz | |
UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86()
Rename the variable to "gPatchSmiCr3" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(). This
lets us remove the binary (DB) encoding of some instructions in
"SmiEntry.nasm".
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 6 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 4 | ||||
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 6 |
3 files changed, 8 insertions, 8 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index 0ea3c1e449..0023cb328d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -44,7 +44,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gcSmiHandlerTemplate)
global ASM_PFX(gcSmiHandlerSize)
-global ASM_PFX(gSmiCr3)
+global ASM_PFX(gPatchSmiCr3)
global ASM_PFX(gPatchSmiStack)
global ASM_PFX(gPatchSmbase)
global ASM_PFX(mXdSupported)
@@ -93,8 +93,8 @@ ASM_PFX(gPatchSmiStack): jmp ProtFlatMode
ProtFlatMode:
- DB 0xb8 ; mov eax, imm32
-ASM_PFX(gSmiCr3): DD 0
+ mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmiCr3):
mov cr3, eax
;
; Need to test for CR4 specific bit support
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c index f0c2892543..5c2eb9ab6a 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -107,7 +107,7 @@ typedef struct { ///
X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;
X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;
-extern UINT32 gSmiCr3;
+X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;
extern volatile UINT8 gcSmiHandlerTemplate[];
extern CONST UINT16 gcSmiHandlerSize;
@@ -719,7 +719,7 @@ InstallSmiHandler ( //
CpuSmiStack = (UINT32)((UINTN)SmiStack + StackSize - sizeof (UINTN));
PatchInstructionX86 (gPatchSmiStack, CpuSmiStack, 4);
- gSmiCr3 = Cr3;
+ PatchInstructionX86 (gPatchSmiCr3, Cr3, 4);
PatchInstructionX86 (gPatchSmbase, SmBase, 4);
gSmiHandlerIdtr.Base = IdtBase;
gSmiHandlerIdtr.Limit = (UINT16)(IdtSize - 1);
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm index 9cfa8e7fc8..9971ae6f06 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -56,7 +56,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gPatchSmbase)
global ASM_PFX(mXdSupported)
global ASM_PFX(gPatchSmiStack)
-global ASM_PFX(gSmiCr3)
+global ASM_PFX(gPatchSmiCr3)
global ASM_PFX(gcSmiHandlerTemplate)
global ASM_PFX(gcSmiHandlerSize)
@@ -102,8 +102,8 @@ ASM_PFX(gPatchSmiStack): BITS 64
ProtFlatMode:
- DB 0xb8 ; mov eax, offset gSmiCr3
-ASM_PFX(gSmiCr3): DD 0
+ mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmiCr3):
mov cr3, rax
mov eax, 0x668 ; as cr4.PGE is not set here, refresh cr3
mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
|