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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2020-03-07 10:10:07 +0100 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-03-10 00:19:30 +0000 |
| commit | d93fe5b579091a6d505419cbfe58aa9d62c3b292 (patch) | |
| tree | be182808adbe409fa4c757c8d42a294d66b00e04 | |
| parent | 748fea6279efc20de3fef483deb4b774f3c34906 (diff) | |
| download | edk2-d93fe5b579091a6d505419cbfe58aa9d62c3b292.tar.gz | |
ArmPkg/ArmMmuLib AARCH64: drop pointless page table memory type check
This is the AARCH64 counterpart of commit 1f3b1eb3082206e4, to remove
a pointless check against the memory type of the allocations that the
page tables happened to land in. On ArmV8, we use writeback cacheable
exclusively for all memory.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-Id: <20200307091008.14918-2-ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
| -rw-r--r-- | ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 221175ca65..f2eec71913 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -497,7 +497,6 @@ ArmConfigureMmu ( )
{
VOID* TranslationTable;
- UINT32 TranslationTableAttribute;
UINT64 MaxAddress;
UINTN T0SZ;
UINTN RootTableEntryCount;
@@ -618,18 +617,7 @@ ArmConfigureMmu ( RootTableEntryCount * sizeof(UINT64));
ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64));
- TranslationTableAttribute = TT_ATTR_INDX_INVALID;
while (MemoryTable->Length != 0) {
-
- DEBUG_CODE_BEGIN ();
- // Find the memory attribute for the Translation Table
- if ((UINTN)TranslationTable >= MemoryTable->PhysicalBase &&
- (UINTN)TranslationTable + EFI_PAGE_SIZE <= MemoryTable->PhysicalBase +
- MemoryTable->Length) {
- TranslationTableAttribute = MemoryTable->Attributes;
- }
- DEBUG_CODE_END ();
-
Status = FillTranslationTable (TranslationTable, MemoryTable);
if (EFI_ERROR (Status)) {
goto FREE_TRANSLATION_TABLE;
@@ -637,9 +625,6 @@ ArmConfigureMmu ( MemoryTable++;
}
- ASSERT (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK ||
- TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK);
-
ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) | // mapped to EFI_MEMORY_UC
MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) | // mapped to EFI_MEMORY_WC
MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) | // mapped to EFI_MEMORY_WT
|