diff options
| author | Maurice Ma <maurice.ma@intel.com> | 2016-10-26 11:15:14 -0700 |
|---|---|---|
| committer | Maurice Ma <maurice.ma@intel.com> | 2016-10-26 14:52:49 -0700 |
| commit | 937f5cb6ac65590174379623acd88d4f1caf0c77 (patch) | |
| tree | a01a4c99fd667dbb02d06d95f5c8ed53c69e267c /CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | |
| parent | 200eaa3d7d5595a8a5884e6f1f7c5f0a4aef4a1a (diff) | |
| download | edk2-937f5cb6ac65590174379623acd88d4f1caf0c77.tar.gz | |
CorebootPayloadPkg DSC: Change the section alignment option
The current CorebootPayloadPkg will print the following message
"InsertImageRecord - Section Alignment(0x20) is not 4K" during
boot. It is caused by the section alignment arranged by the linker.
This patch change the alignment to 4K for runtime drivers.
Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
Diffstat (limited to 'CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc')
| -rw-r--r-- | CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc index 16484b1655..c49f05ec8a 100644 --- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc +++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc @@ -90,6 +90,9 @@ INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
################################################################################
#
# SKU Identification section - list of all SKU IDs supported by this Platform.
|