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| author | Kuo, Ted <ted.kuo@intel.com> | 2022-11-09 03:30:57 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-11-11 04:46:39 +0000 |
| commit | 3182843f3bc92599fa2ed4fd13ffd3f75907fe9e (patch) | |
| tree | fbefc5018646a9e888198f0b79b39e4740c7d402 /IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | |
| parent | c8fb7240469b5753773da4fa5710b870b790c363 (diff) | |
| download | edk2-3182843f3bc92599fa2ed4fd13ffd3f75907fe9e.tar.gz | |
IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-T
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4114
1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer
respectively in TempRamInitApi in IA32 FspSecCoreT.
2.Correct inappropriate description in the return value of
AsmGetFspInfoHeader.
3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in
FspHeler.nasm.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ashraf Ali S <ashraf.ali.s@intel.com>
Cc: Chinni B Duggapu <chinni.b.duggapu@intel.com>
Signed-off-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm index 73821ad22a..2cff8b3643 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -594,37 +594,38 @@ ASM_PFX(TempRamInitApi): SAVE_EAX
SAVE_EDX
+ CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
+ SAVE_ECX ; save UPD param to slot 3 in xmm6
+
;
; Sec Platform Init
;
- CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
CALL_MMX ASM_PFX(SecPlatformInit)
cmp eax, 0
jnz TempRamInitExit
; Load microcode
LOAD_ESP
- CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
+ LOAD_ECX
CALL_MMX ASM_PFX(LoadMicrocodeDefault)
- SXMMN xmm6, 3, eax ;Save microcode return status in ECX-SLOT 3 in xmm6.
+ SAVE_UCODE_STATUS ; Save microcode return status in slot 1 in xmm5.
;@note If return value eax is not 0, microcode did not load, but continue and attempt to boot.
; Call Sec CAR Init
LOAD_ESP
- CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
+ LOAD_ECX
CALL_MMX ASM_PFX(SecCarInit)
cmp eax, 0
jnz TempRamInitExit
LOAD_ESP
- CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param
- mov edi, ecx ; Save UPD param to EDI for later code use
+ LOAD_ECX
+ mov edi, ecx ; Save UPD param to EDI for later code use
CALL_MMX ASM_PFX(EstablishStackFsp)
cmp eax, 0
jnz TempRamInitExit
- LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error from ECX-SLOT 3 in xmm6.
- SXMMN xmm6, 3, edi ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 in xmm6.
+ LOAD_UCODE_STATUS ; Restore microcode status if no CAR init error from slot 1 in xmm5.
TempRamInitExit:
mov bl, al ; save al data in bl
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