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| author | Zhiguang Liu <zhiguang.liu@intel.com> | 2024-06-18 16:13:12 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-09-11 05:45:54 +0000 |
| commit | 14c9ba1a2ca64137de148968823dc20988dcaa4c (patch) | |
| tree | eb72fb06f97a282a9b9a97bea54301c57c7d6e45 /IntelFsp2Pkg/FspSecCore/Ia32 | |
| parent | 9a4088777fbe7941664ad9bb2bd78446d223cbf9 (diff) | |
| download | edk2-14c9ba1a2ca64137de148968823dc20988dcaa4c.tar.gz | |
IntelFsp2Pkg: Support FSP API to save and restore page table
A potential issue may happen when FSP creates/changes page table while
bootloader doesn't expect page table being changed in FSP.
Current, FSP API support to save/restore stack, IDT and general purpose
registers. Following the same pattern, add save/restore page table
support to solve this issue.
Note that this feature only impacts FSP API mode, and is controlled
by PCD PcdFspSaveRestorePageTableEnable. For compatibility, the PCD
default value is set as FALSE.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore/Ia32')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 30 | ||||
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 30 |
2 files changed, 58 insertions, 2 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm index 5fa5c03569..e9bf0cbed2 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm @@ -13,6 +13,7 @@ extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
+extern ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
struc FSPM_UPD_COMMON
; FSP_UPD_HEADER {
@@ -64,7 +65,7 @@ extern ASM_PFX(AsmGetFspInfoHeader) extern ASM_PFX(FspMultiPhaseMemInitApiHandler)
STACK_SAVED_EAX_OFFSET EQU 4 * 7 ; size of a general purpose register * eax index
-API_PARAM1_OFFSET EQU 34h ; ApiParam1 [ sub esp,8 + pushad + pushfd + push eax + call]
+API_PARAM1_OFFSET EQU 44h ; ApiParam1 [ sub esp,8 + push cr0/cr3/cr4/EFER + pushad + pushfd + push eax + call]
FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
FSP_HEADER_CFGREG_OFFSET EQU 24h
@@ -153,6 +154,33 @@ NotMultiPhaseMemoryInitApi: cli
pushad
+ ;
+ ; Allocate 4x4 bytes on the stack.
+ ;
+ sub esp, 16
+ cmp byte [dword ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))], 0
+ jz SkipPagetableSave
+
+ add esp, 16
+ ; Save EFER MSR lower 32 bits
+ push ecx
+ push eax
+ mov ecx, 0xC0000080
+ rdmsr
+ mov edx, eax
+ pop eax
+ pop ecx
+ push edx
+
+ ; Save CR registers
+ mov edx, cr4
+ push edx
+ mov edx, cr3
+ push edx
+ mov edx, cr0
+ push edx
+SkipPagetableSave:
+
; Reserve 8 bytes for IDT save/restore
sub esp, 8
sidt [esp]
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm index 861cce4d01..b1623063ef 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -13,6 +13,7 @@ extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))
extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))
extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))
+extern ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
struc FSPM_UPD_COMMON
; FSP_UPD_HEADER {
@@ -62,7 +63,7 @@ extern ASM_PFX(FspApiCommon) extern ASM_PFX(AsmGetFspBaseAddress)
extern ASM_PFX(AsmGetFspInfoHeader)
-API_PARAM1_OFFSET EQU 34h ; ApiParam1 [ sub esp,8 + pushad + pushfd + push eax + call]
+API_PARAM1_OFFSET EQU 44h ; ApiParam1 [ sub esp,8 + push cr0/cr3/cr4/EFER +pushad + pushfd + push eax + call]
FSP_HEADER_IMGBASE_OFFSET EQU 1Ch
FSP_HEADER_CFGREG_OFFSET EQU 24h
@@ -124,6 +125,33 @@ ASM_PFX(FspApiCommonContinue): cli
pushad
+ ;
+ ; Allocate 4x4 bytes on the stack.
+ ;
+ sub esp, 16
+ cmp byte [dword ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))], 0
+ jz SkipPagetableSave
+
+ add esp, 16
+ ; Save EFER MSR lower 32-bit
+ push ecx
+ push eax
+ mov ecx, 0xC0000080
+ rdmsr
+ mov edx, eax
+ pop eax
+ pop ecx
+ push edx
+
+ ; Save CR registers
+ mov edx, cr4
+ push edx
+ mov edx, cr3
+ push edx
+ mov edx, cr0
+ push edx
+
+SkipPagetableSave:
; Reserve 8 bytes for IDT save/restore
sub esp, 8
sidt [esp]
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