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| author | S, Ashraf Ali <ashraf.ali.s@intel.com> | 2021-12-16 16:10:20 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-20 03:42:50 +0000 |
| commit | de9e5b7dc721d4ca319c0455cf83577347e0abef (patch) | |
| tree | 575718202b16332c5557a66cb3c7837dbcef4f3c /IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | |
| parent | ee1f8262b83dd88b30091e6e81221ff299796099 (diff) | |
| download | edk2-de9e5b7dc721d4ca319c0455cf83577347e0abef.tar.gz | |
IntelFsp2WrapperPkg : FSPM/S UPD data address based on Build Type
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3642
when the module is not building in IA32 mode which will lead to building
error. when a module built-in X64 function pointer will be the size of
64bit width which cannot be fit in 32bit address which will lead to
error. to overcome this issue introducing the 2 new PCD's for the 64bit
modules can consume it. based on the which pcd platform set, use that.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Kuo Ted <ted.kuo@intel.com>
Cc: Duggapu Chinni B <chinni.b.duggapu@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Cc: Digant H Solanki <digant.h.solanki@intel.com>
Cc: Sangeetha V <sangeetha.v@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Ashraf Ali S <ashraf.ali.s@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Diffstat (limited to 'IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c')
| -rw-r--r-- | IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 25 |
1 files changed, 22 insertions, 3 deletions
diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index f7459a90b5..ddee9cd029 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -3,7 +3,7 @@ register TemporaryRamDonePpi to call TempRamExit API, and register MemoryDiscoveredPpi
notify to call FspSiliconInit API.
- Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -182,6 +182,25 @@ FspSiliconInitDoneGetFspHobList ( }
/**
+ Get the FSP S UPD Data address
+
+ @return FSP-S UPD Data Address
+**/
+
+UINTN
+EFIAPI
+GetFspsUpdDataAddress (
+ VOID
+ )
+{
+ if (PcdGet64 (PcdFspsUpdDataAddress64) != 0) {
+ return (UINTN) PcdGet64 (PcdFspsUpdDataAddress64);
+ } else {
+ return (UINTN) PcdGet32 (PcdFspsUpdDataAddress);
+ }
+}
+
+/**
This function is for FSP dispatch mode to perform post FSP-S process.
@param[in] PeiServices Pointer to PEI Services Table.
@@ -283,7 +302,7 @@ PeiMemoryDiscoveredNotify ( return EFI_DEVICE_ERROR;
}
- if ((PcdGet32 (PcdFspsUpdDataAddress) == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {
+ if ((GetFspsUpdDataAddress () == 0) && (FspsHeaderPtr->CfgRegionSize != 0) && (FspsHeaderPtr->CfgRegionOffset != 0)) {
//
// Copy default FSP-S UPD data from Flash
//
@@ -292,7 +311,7 @@ PeiMemoryDiscoveredNotify ( SourceData = (UINTN *)((UINTN)FspsHeaderPtr->ImageBase + (UINTN)FspsHeaderPtr->CfgRegionOffset);
CopyMem (FspsUpdDataPtr, SourceData, (UINTN)FspsHeaderPtr->CfgRegionSize);
} else {
- FspsUpdDataPtr = (FSPS_UPD_COMMON *)PcdGet32 (PcdFspsUpdDataAddress);
+ FspsUpdDataPtr = (FSPS_UPD_COMMON *) GetFspsUpdDataAddress();
ASSERT (FspsUpdDataPtr != NULL);
}
|