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authorRuiyu Ni <ruiyu.ni@intel.com>2019-01-21 23:16:22 +0800
committerRay Ni <ray.ni@intel.com>2019-02-19 17:14:34 +0800
commit13a47cf9251b11d07e25027dc13d3f4a0f5c17ed (patch)
tree79989274ad2c4765c9b7aab97556ad362fcf89b9 /OvmfPkg/build.sh
parenta083afa3fe9e6b7c93d41f775bf443fd2ac6cea8 (diff)
downloadedk2-13a47cf9251b11d07e25027dc13d3f4a0f5c17ed.tar.gz
UefiCpuPkg/MtrrLib: Fix a bug that may wrongly set memory <1MB to UC
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1481 Today's MtrrLib contains a bug, for example: when the original cache setting is WB for [0xF_0000, 0xF_8000) and, a new request to set [0xF_0000, 0xF_4000) to WP, the cache setting for [0xF_4000, 0xF_8000) is reset to UC. The reason is when MtrrLibSetBelow1MBMemoryAttribute() is called the WorkingFixedSettings doesn't contain the actual MSR value stored in hardware, but when writing the fixed MTRRs, the code logic assumes WorkingFixedSettings contains the actual MSR value. The new fix is to change MtrrLibSetBelow1MBMemoryAttribute() to calculate the correct ClearMasks[] and OrMasks[], and use them directly when writing the fixed MTRRs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
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