diff options
| author | Jiaxin Wu <jiaxin.wu@intel.com> | 2024-10-12 14:32:40 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2024-10-16 04:06:42 +0000 |
| commit | a232e0cd2fe2bb882a5dd0cafe322a2899a44d51 (patch) | |
| tree | 392bce4c6a7eb629b202d36360730869e3b23355 /UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | |
| parent | 92c1274467fff3209d3bd29c2ed994b7f2be3efe (diff) | |
| download | edk2-a232e0cd2fe2bb882a5dd0cafe322a2899a44d51.tar.gz | |
UefiCpuPkg/PiSmmCpuDxeSmm: Save and restore CR2 only if SmiProfile enable
A page fault (#PF) that triggers an update to the page table only occurs
if SmiProfile is enabled. Therefore, it is necessary to save and restore
the CR2 register if SmiProfile is configured to be enabled.
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c')
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 20 |
1 files changed, 18 insertions, 2 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 160e33b4ed..f4aa267984 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -851,7 +851,15 @@ SaveCr2 ( OUT UINTN *Cr2
)
{
- *Cr2 = AsmReadCr2 ();
+ //
+ // A page fault (#PF) that triggers an update to the page
+ // table only occurs if SmiProfile is enabled. Therefore, it is
+ // necessary to save the CR2 register if SmiProfile is
+ // configured to be enabled.
+ //
+ if (mSmmProfileEnabled) {
+ *Cr2 = AsmReadCr2 ();
+ }
}
/**
@@ -864,5 +872,13 @@ RestoreCr2 ( IN UINTN Cr2
)
{
- AsmWriteCr2 (Cr2);
+ //
+ // A page fault (#PF) that triggers an update to the page
+ // table only occurs if SmiProfile is enabled. Therefore, it is
+ // necessary to restore the CR2 register if SmiProfile is
+ // configured to be enabled.
+ //
+ if (mSmmProfileEnabled) {
+ AsmWriteCr2 (Cr2);
+ }
}
|