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| author | Edgar Handal <ehandal@nvidia.com> | 2019-02-20 01:06:56 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2019-02-20 09:07:27 +0800 |
| commit | f168816c49e388dcd097dd62d766d63f73aaabb3 (patch) | |
| tree | 4a67cf45d4df3ffc9cb08dff2b7daa9ed843edb4 /UefiCpuPkg/SecCore/SecMain.h | |
| parent | 195f673f6270aaf73dd34b75f1da26451b63c316 (diff) | |
| download | edk2-f168816c49e388dcd097dd62d766d63f73aaabb3.tar.gz | |
MdeModulePkg/SdMmcPciHcDxe: Use 16/32-bit IO widths
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1537
Use 16-bit and 32-bit IO widths for SDMMC MMIO to prevent all register
accesses from being split up into 8-bit accesses.
The SDHCI specification states that the registers shall be accessible in
byte, word, and double word accesses. (SD Host Controller Simplified
Specification 4.20 Section 1.2)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jeff Brasen <jbrasen@nvidia.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Diffstat (limited to 'UefiCpuPkg/SecCore/SecMain.h')
0 files changed, 0 insertions, 0 deletions