diff options
| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:54:18 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | e5efcf8be8a1bf59aa98875787475e3144ee4cef (patch) | |
| tree | f872d2f419303dbd9aa1d3ad745635abffb2f233 /UefiPayloadPkg/UefiPayloadEntry/X64 | |
| parent | 053e878bfb5c9d5eca779789b62891add30b14ba (diff) | |
| download | edk2-e5efcf8be8a1bf59aa98875787475e3144ee4cef.tar.gz | |
UefiPayloadPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the UefiPayloadPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Diffstat (limited to 'UefiPayloadPkg/UefiPayloadEntry/X64')
| -rw-r--r-- | UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c | 31 | ||||
| -rw-r--r-- | UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c | 382 | ||||
| -rw-r--r-- | UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.h | 215 |
3 files changed, 328 insertions, 300 deletions
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c b/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c index dec87ee1ef..346e3feb04 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c +++ b/UefiPayloadPkg/UefiPayloadEntry/X64/DxeLoadFunc.c @@ -15,8 +15,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/HobLib.h>
#include "X64/VirtualMemory.h"
#include "UefiPayloadEntry.h"
-#define STACK_SIZE 0x20000
-
+#define STACK_SIZE 0x20000
/**
Transfers control to DxeCore.
@@ -31,15 +30,15 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
VOID
HandOffToDxeCore (
- IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
- IN EFI_PEI_HOB_POINTERS HobList
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
)
{
- VOID *BaseOfStack;
- VOID *TopOfStack;
- UINTN PageTables;
- VOID *GhcbBase;
- UINTN GhcbSize;
+ VOID *BaseOfStack;
+ VOID *TopOfStack;
+ UINTN PageTables;
+ VOID *GhcbBase;
+ UINTN GhcbSize;
//
// Clear page 0 and mark it as allocated if NULL pointer detection is enabled.
@@ -49,7 +48,6 @@ HandOffToDxeCore ( BuildMemoryAllocationHob (0, EFI_PAGES_TO_SIZE (1), EfiBootServicesData);
}
-
//
// Allocate 128KB for the Stack
//
@@ -60,7 +58,7 @@ HandOffToDxeCore ( // Compute the top of the stack we were allocated. Pre-allocate a UINTN
// for safety.
//
- TopOfStack = (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
+ TopOfStack = (VOID *)((UINTN)BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
//
@@ -74,8 +72,12 @@ HandOffToDxeCore ( //
// Create page table and save PageMapLevel4 to CR3
//
- PageTables = CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS) (UINTN) BaseOfStack, STACK_SIZE,
- (EFI_PHYSICAL_ADDRESS) (UINTN) GhcbBase, GhcbSize);
+ PageTables = CreateIdentityMappingPageTables (
+ (EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack,
+ STACK_SIZE,
+ (EFI_PHYSICAL_ADDRESS)(UINTN)GhcbBase,
+ GhcbSize
+ );
} else {
//
// Set NX for stack feature also require PcdDxeIplBuildPageTables be TRUE
@@ -85,7 +87,6 @@ HandOffToDxeCore ( ASSERT (PcdGetBool (PcdCpuStackGuard) == FALSE);
}
-
if (FeaturePcdGet (PcdDxeIplBuildPageTables)) {
AsmWriteCr3 (PageTables);
}
@@ -93,7 +94,7 @@ HandOffToDxeCore ( //
// Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
//
- UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN) BaseOfStack, STACK_SIZE);
+ UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack, STACK_SIZE);
//
// Transfer the control to the entry point of DxeCore.
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c index a1c4ad6ff4..1272d89413 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c +++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c @@ -35,7 +35,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent //
// Global variable to keep track current available memory used as page table.
//
-PAGE_TABLE_POOL *mPageTablePool = NULL;
+PAGE_TABLE_POOL *mPageTablePool = NULL;
/**
Clear legacy memory located at the first 4K-page, if available.
@@ -48,39 +48,50 @@ PAGE_TABLE_POOL *mPageTablePool = NULL; **/
VOID
ClearFirst4KPage (
- IN VOID *HobStart
+ IN VOID *HobStart
)
{
- EFI_PEI_HOB_POINTERS RscHob;
- EFI_PEI_HOB_POINTERS MemHob;
- BOOLEAN DoClear;
+ EFI_PEI_HOB_POINTERS RscHob;
+ EFI_PEI_HOB_POINTERS MemHob;
+ BOOLEAN DoClear;
RscHob.Raw = HobStart;
MemHob.Raw = HobStart;
- DoClear = FALSE;
+ DoClear = FALSE;
//
// Check if page 0 exists and free
//
- while ((RscHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
- RscHob.Raw)) != NULL) {
- if (RscHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY &&
- RscHob.ResourceDescriptor->PhysicalStart == 0) {
+ while ((RscHob.Raw = GetNextHob (
+ EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,
+ RscHob.Raw
+ )) != NULL)
+ {
+ if ((RscHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&
+ (RscHob.ResourceDescriptor->PhysicalStart == 0))
+ {
DoClear = TRUE;
//
// Make sure memory at 0-4095 has not been allocated.
//
- while ((MemHob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION,
- MemHob.Raw)) != NULL) {
+ while ((MemHob.Raw = GetNextHob (
+ EFI_HOB_TYPE_MEMORY_ALLOCATION,
+ MemHob.Raw
+ )) != NULL)
+ {
if (MemHob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress
- < EFI_PAGE_SIZE) {
+ < EFI_PAGE_SIZE)
+ {
DoClear = FALSE;
break;
}
+
MemHob.Raw = GET_NEXT_HOB (MemHob);
}
+
break;
}
+
RscHob.Raw = GET_NEXT_HOB (RscHob);
}
@@ -119,9 +130,9 @@ IsExecuteDisableBitAvailable ( VOID
)
{
- UINT32 RegEax;
- UINT32 RegEdx;
- BOOLEAN Available;
+ UINT32 RegEax;
+ UINT32 RegEdx;
+ BOOLEAN Available;
Available = FALSE;
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
@@ -172,9 +183,9 @@ EnableExecuteDisableBit ( VOID
)
{
- UINT64 MsrRegisters;
+ UINT64 MsrRegisters;
- MsrRegisters = AsmReadMsr64 (0xC0000080);
+ MsrRegisters = AsmReadMsr64 (0xC0000080);
MsrRegisters |= BIT11;
AsmWriteMsr64 (0xC0000080, MsrRegisters);
}
@@ -195,20 +206,20 @@ EnableExecuteDisableBit ( **/
BOOLEAN
ToSplitPageTable (
- IN EFI_PHYSICAL_ADDRESS Address,
- IN UINTN Size,
- IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize,
- IN EFI_PHYSICAL_ADDRESS GhcbBase,
- IN UINTN GhcbSize
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN UINTN Size,
+ IN EFI_PHYSICAL_ADDRESS StackBase,
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
)
{
- if (IsNullDetectionEnabled () && Address == 0) {
+ if (IsNullDetectionEnabled () && (Address == 0)) {
return TRUE;
}
if (PcdGetBool (PcdCpuStackGuard)) {
- if (StackBase >= Address && StackBase < (Address + Size)) {
+ if ((StackBase >= Address) && (StackBase < (Address + Size))) {
return TRUE;
}
}
@@ -227,6 +238,7 @@ ToSplitPageTable ( return FALSE;
}
+
/**
Initialize a buffer pool for page table use only.
@@ -246,18 +258,18 @@ ToSplitPageTable ( **/
BOOLEAN
InitializePageTablePool (
- IN UINTN PoolPages
+ IN UINTN PoolPages
)
{
- VOID *Buffer;
+ VOID *Buffer;
//
// Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for
// header.
//
PoolPages += 1; // Add one page for header.
- PoolPages = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) *
- PAGE_TABLE_POOL_UNIT_PAGES;
+ PoolPages = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) *
+ PAGE_TABLE_POOL_UNIT_PAGES;
Buffer = AllocateAlignedPages (PoolPages, PAGE_TABLE_POOL_ALIGNMENT);
if (Buffer == NULL) {
DEBUG ((DEBUG_ERROR, "ERROR: Out of aligned pages\r\n"));
@@ -268,19 +280,19 @@ InitializePageTablePool ( // Link all pools into a list for easier track later.
//
if (mPageTablePool == NULL) {
- mPageTablePool = Buffer;
+ mPageTablePool = Buffer;
mPageTablePool->NextPool = mPageTablePool;
} else {
((PAGE_TABLE_POOL *)Buffer)->NextPool = mPageTablePool->NextPool;
- mPageTablePool->NextPool = Buffer;
- mPageTablePool = Buffer;
+ mPageTablePool->NextPool = Buffer;
+ mPageTablePool = Buffer;
}
//
// Reserve one page for pool header.
//
- mPageTablePool->FreePages = PoolPages - 1;
- mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1);
+ mPageTablePool->FreePages = PoolPages - 1;
+ mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1);
return TRUE;
}
@@ -304,10 +316,10 @@ InitializePageTablePool ( **/
VOID *
AllocatePageTableMemory (
- IN UINTN Pages
+ IN UINTN Pages
)
{
- VOID *Buffer;
+ VOID *Buffer;
if (Pages == 0) {
return NULL;
@@ -316,8 +328,9 @@ AllocatePageTableMemory ( //
// Renew the pool if necessary.
//
- if (mPageTablePool == NULL ||
- Pages > mPageTablePool->FreePages) {
+ if ((mPageTablePool == NULL) ||
+ (Pages > mPageTablePool->FreePages))
+ {
if (!InitializePageTablePool (Pages)) {
return NULL;
}
@@ -325,8 +338,8 @@ AllocatePageTableMemory ( Buffer = (UINT8 *)mPageTablePool + mPageTablePool->Offset;
- mPageTablePool->Offset += EFI_PAGES_TO_SIZE (Pages);
- mPageTablePool->FreePages -= Pages;
+ mPageTablePool->Offset += EFI_PAGES_TO_SIZE (Pages);
+ mPageTablePool->FreePages -= Pages;
return Buffer;
}
@@ -344,18 +357,18 @@ AllocatePageTableMemory ( **/
VOID
Split2MPageTo4K (
- IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
- IN OUT UINT64 *PageEntry2M,
- IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize,
- IN EFI_PHYSICAL_ADDRESS GhcbBase,
- IN UINTN GhcbSize
+ IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
+ IN OUT UINT64 *PageEntry2M,
+ IN EFI_PHYSICAL_ADDRESS StackBase,
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
)
{
- EFI_PHYSICAL_ADDRESS PhysicalAddress4K;
- UINTN IndexOfPageTableEntries;
- PAGE_TABLE_4K_ENTRY *PageTableEntry;
- UINT64 AddressEncMask;
+ EFI_PHYSICAL_ADDRESS PhysicalAddress4K;
+ UINTN IndexOfPageTableEntries;
+ PAGE_TABLE_4K_ENTRY *PageTableEntry;
+ UINT64 AddressEncMask;
//
// Make sure AddressEncMask is contained to smallest supported address field
@@ -368,14 +381,14 @@ Split2MPageTo4K ( //
// Fill in 2M page entry.
//
- *PageEntry2M = (UINT64) (UINTN) PageTableEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
+ *PageEntry2M = (UINT64)(UINTN)PageTableEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
PhysicalAddress4K = PhysicalAddress;
for (IndexOfPageTableEntries = 0; IndexOfPageTableEntries < 512; IndexOfPageTableEntries++, PageTableEntry++, PhysicalAddress4K += SIZE_4KB) {
//
// Fill in the Page Table entries
//
- PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K;
+ PageTableEntry->Uint64 = (UINT64)PhysicalAddress4K;
//
// The GHCB range consists of two pages per CPU, the GHCB and a
@@ -383,24 +396,28 @@ Split2MPageTo4K ( // unencrypted page while the per-CPU variable page needs to be
// mapped encrypted. These pages alternate in assignment.
//
- if ((GhcbBase == 0)
- || (PhysicalAddress4K < GhcbBase)
- || (PhysicalAddress4K >= GhcbBase + GhcbSize)
- || (((PhysicalAddress4K - GhcbBase) & SIZE_4KB) != 0)) {
+ if ( (GhcbBase == 0)
+ || (PhysicalAddress4K < GhcbBase)
+ || (PhysicalAddress4K >= GhcbBase + GhcbSize)
+ || (((PhysicalAddress4K - GhcbBase) & SIZE_4KB) != 0))
+ {
PageTableEntry->Uint64 |= AddressEncMask;
}
+
PageTableEntry->Bits.ReadWrite = 1;
- if ((IsNullDetectionEnabled () && PhysicalAddress4K == 0) ||
- (PcdGetBool (PcdCpuStackGuard) && PhysicalAddress4K == StackBase)) {
+ if ((IsNullDetectionEnabled () && (PhysicalAddress4K == 0)) ||
+ (PcdGetBool (PcdCpuStackGuard) && (PhysicalAddress4K == StackBase)))
+ {
PageTableEntry->Bits.Present = 0;
} else {
PageTableEntry->Bits.Present = 1;
}
- if (PcdGetBool (PcdSetNxForStack)
- && (PhysicalAddress4K >= StackBase)
- && (PhysicalAddress4K < StackBase + StackSize)) {
+ if ( PcdGetBool (PcdSetNxForStack)
+ && (PhysicalAddress4K >= StackBase)
+ && (PhysicalAddress4K < StackBase + StackSize))
+ {
//
// Set Nx bit for stack.
//
@@ -422,18 +439,18 @@ Split2MPageTo4K ( **/
VOID
Split1GPageTo2M (
- IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
- IN OUT UINT64 *PageEntry1G,
- IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize,
- IN EFI_PHYSICAL_ADDRESS GhcbBase,
- IN UINTN GhcbSize
+ IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
+ IN OUT UINT64 *PageEntry1G,
+ IN EFI_PHYSICAL_ADDRESS StackBase,
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
)
{
- EFI_PHYSICAL_ADDRESS PhysicalAddress2M;
- UINTN IndexOfPageDirectoryEntries;
- PAGE_TABLE_ENTRY *PageDirectoryEntry;
- UINT64 AddressEncMask;
+ EFI_PHYSICAL_ADDRESS PhysicalAddress2M;
+ UINTN IndexOfPageDirectoryEntries;
+ PAGE_TABLE_ENTRY *PageDirectoryEntry;
+ UINT64 AddressEncMask;
//
// Make sure AddressEncMask is contained to smallest supported address field
@@ -446,7 +463,7 @@ Split1GPageTo2M ( //
// Fill in 1G page entry.
//
- *PageEntry1G = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
+ *PageEntry1G = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;
PhysicalAddress2M = PhysicalAddress;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) {
@@ -454,15 +471,15 @@ Split1GPageTo2M ( //
// Need to split this 2M page that covers NULL or stack range.
//
- Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, StackBase, StackSize, GhcbBase, GhcbSize);
+ Split2MPageTo4K (PhysicalAddress2M, (UINT64 *)PageDirectoryEntry, StackBase, StackSize, GhcbBase, GhcbSize);
} else {
//
// Fill in the Page Directory entries
//
- PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress2M | AddressEncMask;
+ PageDirectoryEntry->Uint64 = (UINT64)PhysicalAddress2M | AddressEncMask;
PageDirectoryEntry->Bits.ReadWrite = 1;
- PageDirectoryEntry->Bits.Present = 1;
- PageDirectoryEntry->Bits.MustBe1 = 1;
+ PageDirectoryEntry->Bits.Present = 1;
+ PageDirectoryEntry->Bits.MustBe1 = 1;
}
}
}
@@ -477,9 +494,9 @@ Split1GPageTo2M ( **/
VOID
SetPageTablePoolReadOnly (
- IN UINTN PageTableBase,
- IN EFI_PHYSICAL_ADDRESS Address,
- IN BOOLEAN Level4Paging
+ IN UINTN PageTableBase,
+ IN EFI_PHYSICAL_ADDRESS Address,
+ IN BOOLEAN Level4Paging
)
{
UINTN Index;
@@ -519,13 +536,13 @@ SetPageTablePoolReadOnly ( LevelSize[3] = SIZE_1GB;
LevelSize[4] = SIZE_512GB;
- AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
- PAGING_1G_ADDRESS_MASK_64;
- PageTable = (UINT64 *)(UINTN)PageTableBase;
- PoolUnitSize = PAGE_TABLE_POOL_UNIT_SIZE;
+ AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
+ PAGING_1G_ADDRESS_MASK_64;
+ PageTable = (UINT64 *)(UINTN)PageTableBase;
+ PoolUnitSize = PAGE_TABLE_POOL_UNIT_SIZE;
for (Level = (Level4Paging) ? 4 : 3; Level > 0; --Level) {
- Index = ((UINTN)RShiftU64 (Address, LevelShift[Level]));
+ Index = ((UINTN)RShiftU64 (Address, LevelShift[Level]));
Index &= PAGING_PAE_INDEX_MASK;
PageAttr = PageTable[Index];
@@ -553,14 +570,13 @@ SetPageTablePoolReadOnly ( ASSERT (Index < EFI_PAGE_SIZE/sizeof (UINT64));
PageTable[Index] &= ~(UINT64)IA32_PG_RW;
- PoolUnitSize -= LevelSize[Level];
+ PoolUnitSize -= LevelSize[Level];
++Index;
}
}
break;
-
} else {
//
// The smaller granularity of page must be needed.
@@ -572,18 +588,20 @@ SetPageTablePoolReadOnly ( PhysicalAddress = PageAttr & LevelMask[Level];
for (EntryIndex = 0;
- EntryIndex < EFI_PAGE_SIZE/sizeof (UINT64);
- ++EntryIndex) {
+ EntryIndex < EFI_PAGE_SIZE/sizeof (UINT64);
+ ++EntryIndex)
+ {
NewPageTable[EntryIndex] = PhysicalAddress | AddressEncMask |
IA32_PG_P | IA32_PG_RW;
if (Level > 2) {
NewPageTable[EntryIndex] |= IA32_PG_PS;
}
+
PhysicalAddress += LevelSize[Level - 1];
}
PageTable[Index] = (UINT64)(UINTN)NewPageTable | AddressEncMask |
- IA32_PG_P | IA32_PG_RW;
+ IA32_PG_P | IA32_PG_RW;
PageTable = NewPageTable;
}
}
@@ -598,14 +616,14 @@ SetPageTablePoolReadOnly ( **/
VOID
EnablePageTableProtection (
- IN UINTN PageTableBase,
- IN BOOLEAN Level4Paging
+ IN UINTN PageTableBase,
+ IN BOOLEAN Level4Paging
)
{
- PAGE_TABLE_POOL *HeadPool;
- PAGE_TABLE_POOL *Pool;
- UINT64 PoolSize;
- EFI_PHYSICAL_ADDRESS Address;
+ PAGE_TABLE_POOL *HeadPool;
+ PAGE_TABLE_POOL *Pool;
+ UINT64 PoolSize;
+ EFI_PHYSICAL_ADDRESS Address;
if (mPageTablePool == NULL) {
return;
@@ -615,14 +633,14 @@ EnablePageTableProtection ( // Disable write protection, because we need to mark page table to be write
// protected.
//
- AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);
+ AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);
//
// SetPageTablePoolReadOnly might update mPageTablePool. It's safer to
// remember original one in advance.
//
HeadPool = mPageTablePool;
- Pool = HeadPool;
+ Pool = HeadPool;
do {
Address = (EFI_PHYSICAL_ADDRESS)(UINTN)Pool;
PoolSize = Pool->Offset + EFI_PAGES_TO_SIZE (Pool->FreePages);
@@ -633,9 +651,9 @@ EnablePageTableProtection ( // protection to them one by one.
//
while (PoolSize > 0) {
- SetPageTablePoolReadOnly(PageTableBase, Address, Level4Paging);
- Address += PAGE_TABLE_POOL_UNIT_SIZE;
- PoolSize -= PAGE_TABLE_POOL_UNIT_SIZE;
+ SetPageTablePoolReadOnly (PageTableBase, Address, Level4Paging);
+ Address += PAGE_TABLE_POOL_UNIT_SIZE;
+ PoolSize -= PAGE_TABLE_POOL_UNIT_SIZE;
}
Pool = Pool->NextPool;
@@ -644,7 +662,7 @@ EnablePageTableProtection ( //
// Enable write protection, after page table attribute updated.
//
- AsmWriteCr0 (AsmReadCr0() | CR0_WP);
+ AsmWriteCr0 (AsmReadCr0 () | CR0_WP);
}
/**
@@ -661,37 +679,37 @@ EnablePageTableProtection ( **/
UINTN
CreateIdentityMappingPageTables (
- IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize,
- IN EFI_PHYSICAL_ADDRESS GhcbBase,
- IN UINTN GhcbSize
+ IN EFI_PHYSICAL_ADDRESS StackBase,
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
)
{
- UINT32 RegEax;
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags;
- UINT32 RegEdx;
- UINT8 PhysicalAddressBits;
- EFI_PHYSICAL_ADDRESS PageAddress;
- UINTN IndexOfPml5Entries;
- UINTN IndexOfPml4Entries;
- UINTN IndexOfPdpEntries;
- UINTN IndexOfPageDirectoryEntries;
- UINT32 NumberOfPml5EntriesNeeded;
- UINT32 NumberOfPml4EntriesNeeded;
- UINT32 NumberOfPdpEntriesNeeded;
- PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel5Entry;
- PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;
- PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;
- PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
- PAGE_TABLE_ENTRY *PageDirectoryEntry;
- UINTN TotalPagesNum;
- UINTN BigPageAddress;
- VOID *Hob;
- BOOLEAN Page5LevelSupport;
- BOOLEAN Page1GSupport;
- PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
- UINT64 AddressEncMask;
- IA32_CR4 Cr4;
+ UINT32 RegEax;
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags;
+ UINT32 RegEdx;
+ UINT8 PhysicalAddressBits;
+ EFI_PHYSICAL_ADDRESS PageAddress;
+ UINTN IndexOfPml5Entries;
+ UINTN IndexOfPml4Entries;
+ UINTN IndexOfPdpEntries;
+ UINTN IndexOfPageDirectoryEntries;
+ UINT32 NumberOfPml5EntriesNeeded;
+ UINT32 NumberOfPml4EntriesNeeded;
+ UINT32 NumberOfPdpEntriesNeeded;
+ PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel5Entry;
+ PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;
+ PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;
+ PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
+ PAGE_TABLE_ENTRY *PageDirectoryEntry;
+ UINTN TotalPagesNum;
+ UINTN BigPageAddress;
+ VOID *Hob;
+ BOOLEAN Page5LevelSupport;
+ BOOLEAN Page1GSupport;
+ PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
+ UINT64 AddressEncMask;
+ IA32_CR4 Cr4;
//
// Set PageMapLevel5Entry to suppress incorrect compiler/analyzer warnings
@@ -704,7 +722,7 @@ CreateIdentityMappingPageTables ( AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;
Page1GSupport = FALSE;
- if (PcdGetBool(PcdUse1GPageTable)) {
+ if (PcdGetBool (PcdUse1GPageTable)) {
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000001) {
AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
@@ -719,12 +737,12 @@ CreateIdentityMappingPageTables ( //
Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
if (Hob != NULL) {
- PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
+ PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;
} else {
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
if (RegEax >= 0x80000008) {
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
- PhysicalAddressBits = (UINT8) RegEax;
+ PhysicalAddressBits = (UINT8)RegEax;
} else {
PhysicalAddressBits = 36;
}
@@ -733,8 +751,12 @@ CreateIdentityMappingPageTables ( Page5LevelSupport = FALSE;
if (PcdGetBool (PcdUse5LevelPageTable)) {
AsmCpuidEx (
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,
- &EcxFlags.Uint32, NULL, NULL
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,
+ NULL,
+ &EcxFlags.Uint32,
+ NULL,
+ NULL
);
if (EcxFlags.Bits.FiveLevelPage != 0) {
Page5LevelSupport = TRUE;
@@ -749,7 +771,7 @@ CreateIdentityMappingPageTables ( // due to either unsupported by HW, or disabled by PCD.
//
ASSERT (PhysicalAddressBits <= 52);
- if (!Page5LevelSupport && PhysicalAddressBits > 48) {
+ if (!Page5LevelSupport && (PhysicalAddressBits > 48)) {
PhysicalAddressBits = 48;
}
@@ -758,19 +780,19 @@ CreateIdentityMappingPageTables ( //
NumberOfPml5EntriesNeeded = 1;
if (PhysicalAddressBits > 48) {
- NumberOfPml5EntriesNeeded = (UINT32) LShiftU64 (1, PhysicalAddressBits - 48);
- PhysicalAddressBits = 48;
+ NumberOfPml5EntriesNeeded = (UINT32)LShiftU64 (1, PhysicalAddressBits - 48);
+ PhysicalAddressBits = 48;
}
NumberOfPml4EntriesNeeded = 1;
if (PhysicalAddressBits > 39) {
- NumberOfPml4EntriesNeeded = (UINT32) LShiftU64 (1, PhysicalAddressBits - 39);
- PhysicalAddressBits = 39;
+ NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, PhysicalAddressBits - 39);
+ PhysicalAddressBits = 39;
}
NumberOfPdpEntriesNeeded = 1;
ASSERT (PhysicalAddressBits > 30);
- NumberOfPdpEntriesNeeded = (UINT32) LShiftU64 (1, PhysicalAddressBits - 30);
+ NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, PhysicalAddressBits - 30);
//
// Pre-allocate big pages to avoid later allocations.
@@ -788,17 +810,22 @@ CreateIdentityMappingPageTables ( TotalPagesNum--;
}
- DEBUG ((DEBUG_INFO, "Pml5=%u Pml4=%u Pdp=%u TotalPage=%Lu\n",
- NumberOfPml5EntriesNeeded, NumberOfPml4EntriesNeeded,
- NumberOfPdpEntriesNeeded, (UINT64)TotalPagesNum));
+ DEBUG ((
+ DEBUG_INFO,
+ "Pml5=%u Pml4=%u Pdp=%u TotalPage=%Lu\n",
+ NumberOfPml5EntriesNeeded,
+ NumberOfPml4EntriesNeeded,
+ NumberOfPdpEntriesNeeded,
+ (UINT64)TotalPagesNum
+ ));
- BigPageAddress = (UINTN) AllocatePageTableMemory (TotalPagesNum);
+ BigPageAddress = (UINTN)AllocatePageTableMemory (TotalPagesNum);
ASSERT (BigPageAddress != 0);
//
// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
//
- PageMap = (VOID *) BigPageAddress;
+ PageMap = (VOID *)BigPageAddress;
if (Page5LevelSupport) {
//
// By architecture only one PageMapLevel5 exists - so lets allocate storage for it.
@@ -806,94 +833,98 @@ CreateIdentityMappingPageTables ( PageMapLevel5Entry = PageMap;
BigPageAddress += SIZE_4KB;
}
- PageAddress = 0;
+
+ PageAddress = 0;
for ( IndexOfPml5Entries = 0
- ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded
- ; IndexOfPml5Entries++) {
+ ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded
+ ; IndexOfPml5Entries++)
+ {
//
// Each PML5 entry points to a page of PML4 entires.
// So lets allocate space for them and fill them in in the IndexOfPml4Entries loop.
// When 5-Level Paging is disabled, below allocation happens only once.
//
- PageMapLevel4Entry = (VOID *) BigPageAddress;
+ PageMapLevel4Entry = (VOID *)BigPageAddress;
BigPageAddress += SIZE_4KB;
if (Page5LevelSupport) {
//
// Make a PML5 Entry
//
- PageMapLevel5Entry->Uint64 = (UINT64) (UINTN) PageMapLevel4Entry | AddressEncMask;
+ PageMapLevel5Entry->Uint64 = (UINT64)(UINTN)PageMapLevel4Entry | AddressEncMask;
PageMapLevel5Entry->Bits.ReadWrite = 1;
PageMapLevel5Entry->Bits.Present = 1;
PageMapLevel5Entry++;
}
for ( IndexOfPml4Entries = 0
- ; IndexOfPml4Entries < (NumberOfPml5EntriesNeeded == 1 ? NumberOfPml4EntriesNeeded : 512)
- ; IndexOfPml4Entries++, PageMapLevel4Entry++) {
+ ; IndexOfPml4Entries < (NumberOfPml5EntriesNeeded == 1 ? NumberOfPml4EntriesNeeded : 512)
+ ; IndexOfPml4Entries++, PageMapLevel4Entry++)
+ {
//
// Each PML4 entry points to a page of Page Directory Pointer entires.
// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.
//
- PageDirectoryPointerEntry = (VOID *) BigPageAddress;
- BigPageAddress += SIZE_4KB;
+ PageDirectoryPointerEntry = (VOID *)BigPageAddress;
+ BigPageAddress += SIZE_4KB;
//
// Make a PML4 Entry
//
- PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;
+ PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;
PageMapLevel4Entry->Bits.ReadWrite = 1;
- PageMapLevel4Entry->Bits.Present = 1;
+ PageMapLevel4Entry->Bits.Present = 1;
if (Page1GSupport) {
- PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;
+ PageDirectory1GEntry = (VOID *)PageDirectoryPointerEntry;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {
if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSize, GhcbBase, GhcbSize)) {
- Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, StackBase, StackSize, GhcbBase, GhcbSize);
+ Split1GPageTo2M (PageAddress, (UINT64 *)PageDirectory1GEntry, StackBase, StackSize, GhcbBase, GhcbSize);
} else {
//
// Fill in the Page Directory entries
//
- PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;
+ PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;
PageDirectory1GEntry->Bits.ReadWrite = 1;
- PageDirectory1GEntry->Bits.Present = 1;
- PageDirectory1GEntry->Bits.MustBe1 = 1;
+ PageDirectory1GEntry->Bits.Present = 1;
+ PageDirectory1GEntry->Bits.MustBe1 = 1;
}
}
} else {
for ( IndexOfPdpEntries = 0
- ; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512)
- ; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {
+ ; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512)
+ ; IndexOfPdpEntries++, PageDirectoryPointerEntry++)
+ {
//
// Each Directory Pointer entries points to a page of Page Directory entires.
// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.
//
- PageDirectoryEntry = (VOID *) BigPageAddress;
- BigPageAddress += SIZE_4KB;
+ PageDirectoryEntry = (VOID *)BigPageAddress;
+ BigPageAddress += SIZE_4KB;
//
// Fill in a Page Directory Pointer Entries
//
- PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;
+ PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;
PageDirectoryPointerEntry->Bits.ReadWrite = 1;
- PageDirectoryPointerEntry->Bits.Present = 1;
+ PageDirectoryPointerEntry->Bits.Present = 1;
for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {
if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackSize, GhcbBase, GhcbSize)) {
//
// Need to split this 2M page that covers NULL or stack range.
//
- Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry, StackBase, StackSize, GhcbBase, GhcbSize);
+ Split2MPageTo4K (PageAddress, (UINT64 *)PageDirectoryEntry, StackBase, StackSize, GhcbBase, GhcbSize);
} else {
//
// Fill in the Page Directory entries
//
- PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;
+ PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;
PageDirectoryEntry->Bits.ReadWrite = 1;
- PageDirectoryEntry->Bits.Present = 1;
- PageDirectoryEntry->Bits.MustBe1 = 1;
+ PageDirectoryEntry->Bits.Present = 1;
+ PageDirectoryEntry->Bits.MustBe1 = 1;
}
}
}
@@ -901,7 +932,7 @@ CreateIdentityMappingPageTables ( //
// Fill with null entry for unused PDPTE
//
- ZeroMem (PageDirectoryPointerEntry, (512 - IndexOfPdpEntries) * sizeof(PAGE_MAP_AND_DIRECTORY_POINTER));
+ ZeroMem (PageDirectoryPointerEntry, (512 - IndexOfPdpEntries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER));
}
}
@@ -912,7 +943,7 @@ CreateIdentityMappingPageTables ( }
if (Page5LevelSupport) {
- Cr4.UintN = AsmReadCr4 ();
+ Cr4.UintN = AsmReadCr4 ();
Cr4.Bits.LA57 = 1;
AsmWriteCr4 (Cr4.UintN);
//
@@ -936,4 +967,3 @@ CreateIdentityMappingPageTables ( return (UINTN)PageMap;
}
-
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.h b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.h index 6b7c38a441..616ebe42b0 100644 --- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.h +++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.h @@ -13,38 +13,37 @@ Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+
#ifndef _VIRTUAL_MEMORY_H_
#define _VIRTUAL_MEMORY_H_
-
-#define SYS_CODE64_SEL 0x38
-
+#define SYS_CODE64_SEL 0x38
#pragma pack(1)
typedef union {
struct {
- UINT32 LimitLow : 16;
- UINT32 BaseLow : 16;
- UINT32 BaseMid : 8;
- UINT32 Type : 4;
- UINT32 System : 1;
- UINT32 Dpl : 2;
- UINT32 Present : 1;
- UINT32 LimitHigh : 4;
- UINT32 Software : 1;
- UINT32 Reserved : 1;
- UINT32 DefaultSize : 1;
- UINT32 Granularity : 1;
- UINT32 BaseHigh : 8;
+ UINT32 LimitLow : 16;
+ UINT32 BaseLow : 16;
+ UINT32 BaseMid : 8;
+ UINT32 Type : 4;
+ UINT32 System : 1;
+ UINT32 Dpl : 2;
+ UINT32 Present : 1;
+ UINT32 LimitHigh : 4;
+ UINT32 Software : 1;
+ UINT32 Reserved : 1;
+ UINT32 DefaultSize : 1;
+ UINT32 Granularity : 1;
+ UINT32 BaseHigh : 8;
} Bits;
- UINT64 Uint64;
+ UINT64 Uint64;
} IA32_GDT;
typedef struct {
- IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;
- UINT32 Offset32To63;
- UINT32 Reserved;
+ IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;
+ UINT32 Offset32To63;
+ UINT32 Reserved;
} X64_IDT_GATE_DESCRIPTOR;
//
@@ -54,18 +53,18 @@ typedef struct { typedef union {
struct {
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
- UINT64 Reserved:1; // Reserved
- UINT64 MustBeZero:2; // Must Be Zero
- UINT64 Available:3; // Available for use by system software
- UINT64 PageTableBaseAddress:40; // Page Table Base Address
- UINT64 AvabilableHigh:11; // Available for use by system software
- UINT64 Nx:1; // No Execute bit
+ UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
+ UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
+ UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
+ UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
+ UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
+ UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
+ UINT64 Reserved : 1; // Reserved
+ UINT64 MustBeZero : 2; // Must Be Zero
+ UINT64 Available : 3; // Available for use by system software
+ UINT64 PageTableBaseAddress : 40; // Page Table Base Address
+ UINT64 AvabilableHigh : 11; // Available for use by system software
+ UINT64 Nx : 1; // No Execute bit
} Bits;
UINT64 Uint64;
} PAGE_MAP_AND_DIRECTORY_POINTER;
@@ -75,19 +74,19 @@ typedef union { //
typedef union {
struct {
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
- UINT64 PAT:1; //
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
- UINT64 Available:3; // Available for use by system software
- UINT64 PageTableBaseAddress:40; // Page Table Base Address
- UINT64 AvabilableHigh:11; // Available for use by system software
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
+ UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
+ UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
+ UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
+ UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
+ UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
+ UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
+ UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page
+ UINT64 PAT : 1; //
+ UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
+ UINT64 Available : 3; // Available for use by system software
+ UINT64 PageTableBaseAddress : 40; // Page Table Base Address
+ UINT64 AvabilableHigh : 11; // Available for use by system software
+ UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution
} Bits;
UINT64 Uint64;
} PAGE_TABLE_4K_ENTRY;
@@ -97,21 +96,21 @@ typedef union { //
typedef union {
struct {
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
- UINT64 MustBe1:1; // Must be 1
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
- UINT64 Available:3; // Available for use by system software
- UINT64 PAT:1; //
- UINT64 MustBeZero:8; // Must be zero;
- UINT64 PageTableBaseAddress:31; // Page Table Base Address
- UINT64 AvabilableHigh:11; // Available for use by system software
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
+ UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
+ UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
+ UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
+ UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
+ UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
+ UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
+ UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page
+ UINT64 MustBe1 : 1; // Must be 1
+ UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
+ UINT64 Available : 3; // Available for use by system software
+ UINT64 PAT : 1; //
+ UINT64 MustBeZero : 8; // Must be zero;
+ UINT64 PageTableBaseAddress : 31; // Page Table Base Address
+ UINT64 AvabilableHigh : 11; // Available for use by system software
+ UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution
} Bits;
UINT64 Uint64;
} PAGE_TABLE_ENTRY;
@@ -121,45 +120,45 @@ typedef union { //
typedef union {
struct {
- UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory
- UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write
- UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User
- UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching
- UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached
- UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
- UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page
- UINT64 MustBe1:1; // Must be 1
- UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
- UINT64 Available:3; // Available for use by system software
- UINT64 PAT:1; //
- UINT64 MustBeZero:17; // Must be zero;
- UINT64 PageTableBaseAddress:22; // Page Table Base Address
- UINT64 AvabilableHigh:11; // Available for use by system software
- UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution
+ UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory
+ UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write
+ UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User
+ UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching
+ UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached
+ UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)
+ UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page
+ UINT64 MustBe1 : 1; // Must be 1
+ UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
+ UINT64 Available : 3; // Available for use by system software
+ UINT64 PAT : 1; //
+ UINT64 MustBeZero : 17; // Must be zero;
+ UINT64 PageTableBaseAddress : 22; // Page Table Base Address
+ UINT64 AvabilableHigh : 11; // Available for use by system software
+ UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution
} Bits;
UINT64 Uint64;
} PAGE_TABLE_1G_ENTRY;
#pragma pack()
-#define CR0_WP BIT16
+#define CR0_WP BIT16
-#define IA32_PG_P BIT0
-#define IA32_PG_RW BIT1
-#define IA32_PG_PS BIT7
+#define IA32_PG_P BIT0
+#define IA32_PG_RW BIT1
+#define IA32_PG_PS BIT7
-#define PAGING_PAE_INDEX_MASK 0x1FF
+#define PAGING_PAE_INDEX_MASK 0x1FF
-#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
-#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
-#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
+#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull
+#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
+#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
-#define PAGING_L1_ADDRESS_SHIFT 12
-#define PAGING_L2_ADDRESS_SHIFT 21
-#define PAGING_L3_ADDRESS_SHIFT 30
-#define PAGING_L4_ADDRESS_SHIFT 39
+#define PAGING_L1_ADDRESS_SHIFT 12
+#define PAGING_L2_ADDRESS_SHIFT 21
+#define PAGING_L3_ADDRESS_SHIFT 30
+#define PAGING_L4_ADDRESS_SHIFT 39
-#define PAGING_PML4E_NUMBER 4
+#define PAGING_PML4E_NUMBER 4
#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB
#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB
@@ -168,9 +167,9 @@ typedef union { (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
typedef struct {
- VOID *NextPool;
- UINTN Offset;
- UINTN FreePages;
+ VOID *NextPool;
+ UINTN Offset;
+ UINTN FreePages;
} PAGE_TABLE_POOL;
/**
@@ -207,12 +206,12 @@ EnableExecuteDisableBit ( **/
VOID
Split2MPageTo4K (
- IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
- IN OUT UINT64 *PageEntry2M,
- IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize,
- IN EFI_PHYSICAL_ADDRESS GhcbBase,
- IN UINTN GhcbSize
+ IN EFI_PHYSICAL_ADDRESS PhysicalAddress,
+ IN OUT UINT64 *PageEntry2M,
+ IN EFI_PHYSICAL_ADDRESS StackBase,
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbSize
);
/**
@@ -229,13 +228,12 @@ Split2MPageTo4K ( **/
UINTN
CreateIdentityMappingPageTables (
- IN EFI_PHYSICAL_ADDRESS StackBase,
- IN UINTN StackSize,
- IN EFI_PHYSICAL_ADDRESS GhcbBase,
- IN UINTN GhcbkSize
+ IN EFI_PHYSICAL_ADDRESS StackBase,
+ IN UINTN StackSize,
+ IN EFI_PHYSICAL_ADDRESS GhcbBase,
+ IN UINTN GhcbkSize
);
-
/**
Fix up the vector number in the vector code.
@@ -247,11 +245,10 @@ CreateIdentityMappingPageTables ( VOID
EFIAPI
AsmVectorFixup (
- VOID *VectorBase,
- UINT8 VectorNum
+ VOID *VectorBase,
+ UINT8 VectorNum
);
-
/**
Get the information of vector template.
@@ -278,7 +275,7 @@ AsmGetVectorTemplatInfo ( **/
VOID
ClearFirst4KPage (
- IN VOID *HobStart
+ IN VOID *HobStart
);
/**
@@ -301,8 +298,8 @@ IsNullDetectionEnabled ( **/
VOID
EnablePageTableProtection (
- IN UINTN PageTableBase,
- IN BOOLEAN Level4Paging
+ IN UINTN PageTableBase,
+ IN BOOLEAN Level4Paging
);
/**
@@ -324,7 +321,7 @@ EnablePageTableProtection ( **/
VOID *
AllocatePageTableMemory (
- IN UINTN Pages
+ IN UINTN Pages
);
#endif
|