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* UefiPayloadPkg: Add StackCheckLib to fix FIT build issueAjan Zhong11 days1-0/+1
| | | | | | | | | | Commit efbf5ed moves StackCheckLibStaticInit to StackCheckLib, and each SEC module has a dependency on StackCheckLib now. Add StackCheckLib in FitUniversalPayloadEntry.inf to fix build issue. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* MdePkg: Move StackCheckLibStaticInit to StackCheckLibOliver Smith-Denny2025-02-072-0/+2
| | | | | | | | | | | | | | | This commit oves StackCheckLib from a NULL lib to an instance of StackCheckLib. This requires every entry point to add a library dependency on StackCheckLib. It also requires every SEC module to have a dependency on StackCheckLib because there is no standard SEC entry point. It allows for greater flexibility for a platform to apply stack cookies and simplifies DSC logic. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
* UefiPayloadPkg: Revert 4KB alignment of CLANGDWARF buildChasel Chiu2025-02-031-1/+0
| | | | | | | | | With the latest GccBase.lds combining with CLANG build, there is no need to enforce 4KB alignment of in UPL CLANGDWARF build. This reverts commit b3bfb8f22d43bd9577df85bec20e75eb2f659990. Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiPayloadPkg: Update Elf segment/section syncup processChasel Chiu2025-02-021-13/+58
| | | | | | | | | | Original ELF segment/section syncup process having layout assumption which has caused build failure when layout changing. New process will parse both existing segments and sections firstly to support different layout. Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiPayloadPkg: Add 4KB align to CLANGDWARF build.Chasel Chiu2025-01-251-0/+1
| | | | | | | | | | After commit aca75d3 the PayloadEntry ELF header will miss dynamic section which caused PEI_ASSERT in PayloadLoader rebasing code. This commit adding common-page-size=0x1000 to CLANGDWARF_DLINK_FLAGS to overcome the ELF header generation issue. Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiPayloadpkg Add Missing part backLinus Liu2024-12-301-0/+8
| | | | | | Add back reg attribute of pcirootbridge Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg ：Update RetrieveMultiSegmentInfoFromHobLinus Liu2024-12-301-13/+66
| | | | | | | | | Merge the PCI root bridge with the same segment address within one. PciSegment element. UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Align base address for ACPI regionAjan Zhong2024-12-251-1/+8
| | | | | | | | | | | | In platform which support ACPI 2.0 only, the base address of ACPI region is not page aligned. This unalinged base address leads to failure at BuildMemoryAllocationHob when parsing ACPI node in FdtParserLib, before building gUniversalPayloadAcpiTableGuid GUID HOB. Align base address of ACPI region down to EFI_PAGE_SIZE to make sure base address always aligned. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg: Set PixelsPerScanLine property in GraphicInfo HOBAjan Zhong2024-12-241-0/+3
| | | | | | | | | | | | PixelsPerScanLine is required in some UEFI capable OS distribution. To align with simple-framebuffer definition in kernel Documentation: devicetree/bindings/display/simple-framebuffer.txt, no property node will be introduced for PixelsPerScanLine. Set value of PixelsPerScanLine to HorizontalResolution, as they are identical in most cases. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg: Fix the issue detected by UncrustifyGuo Dong2024-12-191-44/+48
| | | | Signed-off-by: Guo Dong <guo.dong@intel.com>
* UefiPayloadPkg: Enhance universal payload buildGuo Dong2024-12-191-7/+8
| | | | | | | If there is no relocation in the payload it would build failure. This will fix the build failure. Signed-off-by: Guo Dong <guo.dong@intel.com>
* UefiPayloadPkg: Enhance Universal payload serial port nodeGuo Dong2024-12-191-33/+77
| | | | | | | | | | Current implementation only supports serial port sub-node under PCI root bridge node. This enhancement support serial port node regardless it is under root node or PCI root bridge node using a single FDT passing function. Signed-off-by: Guo Dong <guo.dong@intel.com>
* UefiPayloadPkg: Update ReadUnaligned64 in ACPI parsingAjan Zhong2024-12-091-1/+1
| | | | | | | | | | | | | | | According to ACPI Specification, 64 bit physical address of the XSDT provides indentical functionality to the RSDT but accommodates physical address of description headers that are larger than 32 bits. In this case physical address of XSDT table is 64 bit aligned, however size of ACPI description tabled header is not 64 bit aligned. It leads to the entry of other description headers are not 64 bit aligned. In AARCH64 architecture, deference non-aligned 64 bit address to fetch 64-bit data will trigger Alignment fault. Use ReadUnaligned64 method to fix this unaligned data access issue. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg: Update FDT parser logic for unaligned data accessAjan Zhong2024-12-092-10/+10
| | | | | | | | If alignment check is enabled in AARCH64 platform, FDT parser might dereference non-aligned 64-bit address to fetch 64-bit data. Use unaligned data read to avoid triggering unaligned data access. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg: Add AARCH64 support on FdtParserLibAjan Zhong2024-12-091-2/+2
| | | | | | Add AARCH64 support on FdtParserLib. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg/UefiPayloadEntry: Fix PT protection in 5 level pagingedk2-stable202411Ning Feng2024-11-173-28/+34
| | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4873 Currently the function does not cover the 5 level paging case. it will casued pagetable protection region set incorrectly. This patch do the enhancemant and with the patch protection region has been set correctly. Signed-off-by: Ning Feng <ning.feng@intel.com> Cc: Ray Ni <ray.ni@intel.com>
* MdePkg: MdeLibs.dsc.inc: Apply StackCheckLibNull to All Module TypesOliver Smith-Denny2024-11-131-3/+0
| | | | | | | | | | | | | | | Now that the ResetVectors are USER_DEFINED modules, they will not be linked against StackCheckLibNull, which were the only modules causing issues. So, we can now remove the kludge we had before and the requirement for every DSC to include StackCheckLibNull for SEC modules and just apply StackCheckLibNull globally. This also changes every DSC to drop the SEC definition of StackCheckLibNull. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* UefiPayloadPkg ：ACPI memory nodeLinus Liu2024-10-311-1/+22
| | | | | | | | | There are couples of gUniversalPayloadAcpiTableGuid in payload , only build one gUniversalPayloadAcpiTableGuid hob and acpi memory hob. when the reserved memory address matched the rsdp. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg：Add SMBIOS node.Linus Liu2024-10-314-25/+54
| | | | | | | Per other platform request , need to add SMBIOS device node into FDT. In the current phase(1) , only supporting SM3EntryPoint structure. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Modify PCI root reg .Linus Liu2024-10-311-4/+14
| | | | | | | Per Spec updated , update DMA Reg property filed with each root bridge bus base and its bus limit. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Add Secure Boot supportSean Rhodes2024-10-094-3/+77
| | | | | | | | | | | | | | | | | | | | Introduce Secure Boot functionality within UefiPayloadPkg by adding necessary modules and configurations. A new build flag, `SECURE_BOOT_ENABLE`, is introduced to control the activation of Secure Boot. This patch also overrides values in SecurityPkg to enforce image verification from all sources. A new FV (`SECURITY_FV`) for security modules is added for components and the firmware volume sizes to accommodate additional Secure Boot components. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Sean Rhodes <sean@starlabs.systems>
* UefiPayloadPkg : Roll back the sequence of gEfiEndOfPeiSignalPpiGuid.Linus Liu2024-10-081-1/+42
| | | | | | | | Adjust the sequence of gEfiEndOfPeiSignalPpiGuid notify function when FDT is disabled , or some of notify functions won't work cause the debug message print twice. Signed-off-by: Linus Liu <linus.liu@intel.com>
* MdePkg: consistently use "Property" in BaseFdtLibLeif Lindholm2024-10-022-54/+54
| | | | | | | | | | | There is currently a mix on functions named as Prop or Property. The latter is in majority, and the better fit for tianocore coding style, so rename FdtNodeOffsetByPropValue () and FdtSetProp () for consistency. To avoid breaking bisect, change existing users in UefiPayloadPkg. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg,UefiPayloadPkg: improve BaseFdtLib memreserve helper styleLeif Lindholm2024-10-021-2/+2
| | | | | | | | | | | | | | | | | | FdtNumRsv and FdtGetMemRsv were added for the benefit of UefiPayloadPkg, but their naming matches neither upstream libfdt nor tianocore coding style rules. And there was scope for improvement of the doxygen descriptions as well. These functions currently have only one in-tree user, UefiPayloadPkg FdtParserLib. So rename them more conformant FdtGetNumberOfReserveMapEntries and FdtGetReserveMapEntry and update the description comment blocks, at the same time as updating the existing user. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
* UefiPayloadPkg: Enhance ReadMe.md for ELF and FITGua Guo2024-09-231-23/+31
| | | | | | | Enhance and introduce environment construction and build step for ELF and FIT format payload Signed-off-by: Gua Guo <gua.guo@intel.com>
* UefiPayloadPkg: Add LOCKBOX_SUPPORT in UPL and set it as FALSE in defaultZhou Jianfeng2024-09-231-0/+5
| | | | | | | | | | S3 performance table is saved to LockBox. Without LockBox, S3 performance data will lost. Add LOCKBOX_SUPPORT to optionally select LockBox libary instance, default value is FALSE. Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com>
* UefiPayloadPkg: Align relocation item with specGua Guo2024-09-232-2/+2
| | | | | | | | Currently, FIT Payload data relocation data has some minor error with Universal Payload Specification v0.9.1 section 2.4.3. Signed-off-by: Gua Guo <gua.guo@intel.com>
* Set PcdSerialClockRate from SerialPortInfo in UefiPayloadEntryMatt DeVillier2024-09-202-0/+9
| | | | Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
* UefiPayloadPkg: Move FADT check to consumer coode.Chasel Chiu2024-09-163-9/+7
| | | | | | | | | | | | | | | | | | | ACPI FADT HW register interface fields are optional but current UPL common entry code made it as mandatory which caused compatibility issue on some platforms. Solution is to move those FADT HW register fields check code to consumer code so only ASSERT when those fields are consumed with error. Currently only AcpiTimerLib and ResetSystemLib consuming those register fields so if platforms configured UPL to different library instances the FADT HW register fields are not consumed thus will not cause ASSERT. Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiPayloadPkg: Handle simple reserved ranges from DTDhaval2024-09-141-0/+13
| | | | | | | DT has a way to provide reserved images in a simpler tabular manner. UPL should be able to support that. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Add support for Root bridge parserDhaval2024-09-147-42/+310
| | | | | | | | | | | | | | | | | | | | | In order to properly enable multisegment RB, we need to grab ecam data from the FDT for each bridge. Current UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES struct from MdeModulePkg does not include definition for ecam. In order to maintain backward compatibility and also avoid diverging too much from core, we are going to define a new HOB for UPL segment information and pass it to GetPciSegmentInfo function. Ths function then grabs specifically ecam info from the segment hob along with other rb specific information to create final RB info required by multi segment PCI driver. Additionally we would like to support legacy implementations which rely on ACPIBoard HOB to fill up segment info. So if UplSegmentInfo Hob is not found we try and look for other hob. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiPayloadPkg: Add support for Special Purpose memoryDhaval2024-09-141-0/+5
| | | | | | | | | We need to let UEFI know that there are cetain memory types which are special purpose (CXL/HBM) etc and we may want to avoid using them for UEFI purposes. Hence UPL needs to know about such memory types. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Remove unnecessary ACPI checksDhaval2024-09-141-5/+5
| | | | | | | | | | We do not need to go deep into verifying all ACPI tables at this stage. TODO: Just a simple ACPI header signature check should be good enough. For now just commenting out asserts that mandate one to have various tables which is not applicable to all platforms. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Enable RiscV64 entry point to UPLDhaval2024-09-143-0/+112
| | | | | | | | As per specification we are going to accept only one argument at the entry point which is FDT pointer. Grab that and call the entry point. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UniversalPayload: Add RISC-V support for UPL PCDsDhaval2024-09-143-3/+3
| | | | | | Expose UPL required PCDs for RISC-V Arch Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Parse fdt and create smbios tableDhaval2024-09-141-11/+23
| | | | Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Bugfix: Do not parse NULL nodesDhaval2024-09-141-0/+2
| | | | | | | Not every node has compatible property; avoid parsing nodes which return NULL. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Handle ordering issue with option nodeDhaval2024-09-141-3/+6
| | | | | | | | | | Option node provides info that is to be consumed by during metadata creation for other nodes like root bridge; pci-enum-done etc. Handle that dependency by storing option values in a variable and then apply it during post processing. Ideally such cross node dependency should be avoided in design. Scope for futher improvements. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Add StackCheckLibOliver Smith-Denny2024-09-131-0/+3
| | | | | | Add null implementation of StackCheckLib Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* UefiPayloadPkg/UefiPayloadPkg.ci.yaml: Add PrEval CI configJoey Vagedes2024-09-021-0/+3
| | | | | | | | | | | Adds an entry to the package's CI configuration file that enable policy 5 for stuart_pr_eval. With this Policy, all INFs used by the package are extracted from the provided DSC file and compared against the list of changed *.inf (INF) files in the PR. If there is a match, stuart_pr_eval will specify that this package is affected by the PR and needs to be tested. Signed-off-by: Joey Vagedes <joey.vagedes@gmail.com>
* UefiPayloadPkg: Update UefiPayload driver for FDT support.Linus Liu2024-08-289-258/+325
| | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4786 Add FDT detection and comsume FDT when needed. Move some x86 specific function in the x86 folder. Create HandOffHob via FDT memory node. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Update PayloadLoader to suport FDT.Linus Liu2024-08-286-29/+855
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4786 Create FDT nodes (reserved-memory, serial, pci-rb, options) in FdtPpiNotifyCallback function right after gEfiEndOfPeiSignalPpiGuid. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Add FDT Paser relative LIBs.Linus Liu2024-08-2811-0/+2622
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4786 Add FDTParser and CustomFdtNodePaser to retrive all FDT node and create the relate hobs. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Support Debug function when Hob was not available.Linus Liu2024-08-288-8/+97
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4786 Initialize mUartInfo with PCD for debug message when Hob was not available. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Addd header files for FDT structure and function.Linus Liu2024-08-287-0/+251
| | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4786 Add Library header, DeviceTree hob header and PCD definitions. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Fix some spelling mistakes found by cspellRebecca Cran2024-08-015-7/+7
| | | | | | | | | | | When cspell is installed (via `npm install cspell`), CI checks for spelling mistakes. There are currently a very large number of them: some are genuine mistakes while others are words or acryonyms that cspell doesn't know. Fix a few of the misspellings in UefiPayloadPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
* UefiPayloadPkg:Modify the PCD PcieResizableBar to dynamic PCDKasimX Liu2024-07-121-0/+1
| | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4808 Synchronize the use of the PCD PcieResizableBar attribute state Signed-off-by: KasimX Liu <kasimx.liu@intel.com>
* UefiPayloadPkg/UefiPayloadEntry: Use HobPrintLib to dump HOBsWei6 Xu2024-07-074-326/+20
| | | | | | | | | | | | | Leverage generic HOB print code in MdeModulePkg/Library/HobPrintLib. Print UefiPayload specified GUID HOB info as custom HOB print handler when calling the PrintHobList() interface. Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Wei6 Xu <wei6.xu@intel.com>
* UefiPayloadPkg: Enable UPL FIT build config from cmdlineDhaval2024-06-111-1/+3
| | | | | | | | | | | Provide commandline configuration to select proper platform file. Cc: Gua Guo <gua.guo@intel.com> Cc: Guo Dong <guo.dong@intel.com> Cc: James Lu <james.lu@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Fix LoadDxeCore for payload size > 16MBSebastian Witt2024-06-101-2/+3
| | | | | | | | | | | Fix calculation of first section in FileFindSection for FILE2 headers in UefiPayloadEntry module. Signed-off-by: Sebastian Witt <sebastian.witt@siemens.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com>
generated by cgit (git 2.34.1) at 2025-02-23 03:42:03 +0000