diff options
| -rw-r--r-- | src/arch/riscv/core/zicntr.c | 17 | ||||
| -rw-r--r-- | src/arch/riscv/core/zkr.c | 3 |
2 files changed, 11 insertions, 9 deletions
diff --git a/src/arch/riscv/core/zicntr.c b/src/arch/riscv/core/zicntr.c index 0ba453c75..826f31a68 100644 --- a/src/arch/riscv/core/zicntr.c +++ b/src/arch/riscv/core/zicntr.c @@ -64,7 +64,7 @@ rdtime_low ( void ) { unsigned long time; /* Read low XLEN bits of current time */ - __asm__ ( "rdtime %0" : "=r" ( time ) ); + __asm__ __volatile__ ( "rdtime %0" : "=r" ( time ) ); return time; } @@ -86,14 +86,15 @@ rdtime_scaled ( void ) { /* Read full current time */ #if __riscv_xlen >= 64 - __asm__ ( "rdtime %0" : "=r" ( u.time ) ); + __asm__ __volatile__ ( "rdtime %0" : "=r" ( u.time ) ); #else - __asm__ ( "1:\n\t" - "rdtimeh %1\n\t" - "rdtime %0\n\t" - "rdtimeh %2\n\t" - "bne %1, %2, 1b\n\t" - : "=r" ( u.low ), "=r" ( u.high ), "=r" ( tmp ) ); + __asm__ __volatile__ ( "1:\n\t" + "rdtimeh %1\n\t" + "rdtime %0\n\t" + "rdtimeh %2\n\t" + "bne %1, %2, 1b\n\t" + : "=r" ( u.low ), "=r" ( u.high ), + "=r" ( tmp ) ); #endif /* Scale time to avoid XLEN-bit rollover */ diff --git a/src/arch/riscv/core/zkr.c b/src/arch/riscv/core/zkr.c index 5cb44c2d0..bf1609671 100644 --- a/src/arch/riscv/core/zkr.c +++ b/src/arch/riscv/core/zkr.c @@ -85,7 +85,8 @@ static int zkr_get_noise ( noise_sample_t *noise ) { for ( i = 0 ; i < ZKR_SEED_MAX_RETRY ; i++ ) { /* Read seed CSR */ - __asm__ ( "csrrw %0, seed, zero" : "=r" ( seed ) ); + __asm__ __volatile__ ( "csrrw %0, seed, zero" : + "=r" ( seed ) ); /* Check operationsl state */ if ( ( seed & ZKR_SEED_OPST_MASK ) == ZKR_SEED_OPST_ES16 ) { |