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riscv
Commit message (
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Author
Age
Files
Lines
*
[crypto] Expose shifted out bit from big integer shifts
Michael Brown
10 days
1
-16
/
+20
*
[crypto] Expose carry flag from big integer addition and subtraction
Michael Brown
2024-11-26
1
-16
/
+20
*
[riscv] Check if seed CSR is accessible from S-mode
Michael Brown
2024-10-28
2
-0
/
+82
*
[sbi] Add support for running as a RISC-V SBI payload
Michael Brown
2024-10-28
9
-0
/
+442
*
[riscv] Add missing volatile qualifiers on timer and seed CSR accesses
Michael Brown
2024-10-28
2
-9
/
+11
*
[riscv] Add support for the seed CSR as an entropy source
Michael Brown
2024-10-28
2
-0
/
+111
*
[riscv] Add support for RDTIME as a timer source
Michael Brown
2024-10-28
2
-0
/
+194
*
[riscv] Add support for checking CPU extensions reported via device tree
Michael Brown
2024-10-28
3
-0
/
+117
*
[riscv] Add support for reboot and power off via SBI
Michael Brown
2024-10-22
5
-0
/
+120
*
[riscv] Add support for the SBI debug console
Michael Brown
2024-10-22
3
-0
/
+259
*
[crypto] Use architecture-independent bigint_is_set()
Michael Brown
2024-10-10
1
-19
/
+0
*
[crypto] Rename bigint_rol()/bigint_ror() to bigint_shl()/bigint_shr()
Michael Brown
2024-10-07
1
-4
/
+4
*
[crypto] Eliminate temporary carry space for big integer multiplication
Michael Brown
2024-09-27
1
-10
/
+7
*
[profile] Standardise return type of profile_timestamp()
Michael Brown
2024-09-24
1
-0
/
+28
*
[crypto] Use constant-time big integer multiplication
Michael Brown
2024-09-23
2
-117
/
+38
*
[riscv] Add support for the RISC-V CPU architecture
Michael Brown
2024-09-15
21
-0
/
+1593