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path: root/src/arch/riscv/include/bits
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* [crypto] Expose carry flag from big integer addition and subtractionMichael Brown2024-11-261-16/+20
* [sbi] Add support for running as a RISC-V SBI payloadMichael Brown2024-10-281-0/+14
* [riscv] Add support for the seed CSR as an entropy sourceMichael Brown2024-10-281-0/+1
* [riscv] Add support for RDTIME as a timer sourceMichael Brown2024-10-281-0/+1
* [riscv] Add support for checking CPU extensions reported via device treeMichael Brown2024-10-281-0/+1
* [riscv] Add support for reboot and power off via SBIMichael Brown2024-10-222-0/+16
* [crypto] Use architecture-independent bigint_is_set()Michael Brown2024-10-101-19/+0
* [crypto] Rename bigint_rol()/bigint_ror() to bigint_shl()/bigint_shr()Michael Brown2024-10-071-4/+4
* [crypto] Eliminate temporary carry space for big integer multiplicationMichael Brown2024-09-271-10/+7
* [profile] Standardise return type of profile_timestamp()Michael Brown2024-09-241-0/+28
* [crypto] Use constant-time big integer multiplicationMichael Brown2024-09-231-5/+38
* [riscv] Add support for the RISC-V CPU architectureMichael Brown2024-09-1512-0/+815