diff options
| author | Peng Fan <peng.fan@nxp.com> | 2022-07-26 16:41:11 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-07-26 11:29:01 +0200 |
| commit | feaf8e0cf03ef030ed7ebd6db2fa7a1ad3be25d0 (patch) | |
| tree | 62c2ad092227cecfa9d2bcf4bb6746542379da5e | |
| parent | 86a179703c3b514fffa13aef191f2b86cfc11f8e (diff) | |
| download | u-boot-feaf8e0cf03ef030ed7ebd6db2fa7a1ad3be25d0.tar.gz | |
imx: imx93_evk: Set ARM clock to 1.7Ghz
Set ARM clock to OD frequency 1.7Ghz, since we have set PMIC VDD_SOC
to Overdrive voltage 0.9V
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | arch/arm/include/asm/arch-imx9/clock.h | 4 | ||||
| -rw-r--r-- | arch/arm/mach-imx/imx9/clock.c | 9 | ||||
| -rw-r--r-- | board/freescale/imx93_evk/spl.c | 3 |
3 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h index d96f126a1d1..336d8613181 100644 --- a/arch/arm/include/asm/arch-imx9/clock.h +++ b/arch/arm/include/asm/arch-imx9/clock.h @@ -217,6 +217,8 @@ void dram_pll_init(ulong pll_val); void dram_enable_bypass(ulong clk_val); void dram_disable_bypass(void); +int configure_intpll(enum ccm_clk_src pll, u32 freq); + int ccm_clk_src_on(enum ccm_clk_src oscpll, bool enable); int ccm_clk_src_auto(enum ccm_clk_src oscpll, bool enable); int ccm_clk_src_lpm(enum ccm_clk_src oscpll, bool enable); @@ -238,5 +240,5 @@ int ccm_shared_gpr_tz_access(u32 gpr, bool non_secure, bool user_mode, bool lock void enable_usboh3_clk(unsigned char enable); int set_clk_enet(enum enet_freq type); int set_clk_eqos(enum enet_freq type); - +void set_arm_clk(ulong freq); #endif diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 11371f173f0..04f3116fd1c 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -665,6 +665,15 @@ void dram_disable_bypass(void) /* Switch from DRAM clock root from CCM to PLL */ ccm_shared_gpr_set(SHARED_GPR_DRAM_CLK, SHARED_GPR_DRAM_CLK_SEL_PLL); } + +void set_arm_clk(ulong freq) +{ + /* Increase ARM clock to 1.7Ghz */ + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_CCM); + configure_intpll(ARM_PLL_CLK, 1700000000); + ccm_shared_gpr_set(SHARED_GPR_A55_CLK, SHARED_GPR_A55_CLK_SEL_PLL); +} + #endif int clock_init(void) diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c index ca33f943424..38cfbac6ea6 100644 --- a/board/freescale/imx93_evk/spl.c +++ b/board/freescale/imx93_evk/spl.c @@ -108,6 +108,9 @@ void board_init_f(ulong dummy) } power_init_board(); + /* 1.7GHz */ + set_arm_clk(1700000000); + /* Init power of mix */ soc_power_init(); |