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| author | Bin Meng <bmeng@tinylab.org> | 2023-06-21 23:11:46 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-07-12 13:21:40 +0800 |
| commit | 9675d9202780fd996c00ad34f0360c89376205b3 (patch) | |
| tree | 45a6e78f33e00d2a1bbe996d5895162c7f9dbf05 /board/openpiton | |
| parent | 7f1a30fdeb6b51ddeb8ca8ecbfcc8069721db186 (diff) | |
| download | u-boot-9675d9202780fd996c00ad34f0360c89376205b3.tar.gz | |
riscv: Rename SiFive CLINT to RISC-V ALINT
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Diffstat (limited to 'board/openpiton')
| -rw-r--r-- | board/openpiton/riscv64/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/openpiton/riscv64/Kconfig b/board/openpiton/riscv64/Kconfig index eb0db8a64c8..21da1dc346d 100644 --- a/board/openpiton/riscv64/Kconfig +++ b/board/openpiton/riscv64/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPPORT_SPL imply CPU_RISCV imply RISCV_TIMER - imply SPL_SIFIVE_CLINT + imply SPL_RISCV_ACLINT imply CMD_CPU imply SPL_CPU_SUPPORT imply SPL_SMP |