diff options
| author | Michael Trimarchi <michael@amarulasolutions.com> | 2022-07-20 18:22:11 +0200 |
|---|---|---|
| committer | Michael Trimarchi <michael@amarulasolutions.com> | 2022-07-22 13:29:06 +0200 |
| commit | 3de2cdb71e68140425315e79b1643603e8f33517 (patch) | |
| tree | a0a8e80f768167a5c393eb63a1f9189a82458373 /drivers/mtd/nand/raw/nand_base.c | |
| parent | 2811ed2fb0349dd55b07407b19fbcf1a85c9ac4b (diff) | |
| download | u-boot-3de2cdb71e68140425315e79b1643603e8f33517.tar.gz | |
mtd: nand: Move Toshiba specific init/detection logic in nand_toshiba.c
Upstream linux commit 9b2d61f80b060c.
Move Toshiba specific initialization and detection logic into
nand_toshiba.c. This is part of the "separate vendor specific code from
core" cleanup process.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Diffstat (limited to 'drivers/mtd/nand/raw/nand_base.c')
| -rw-r--r-- | drivers/mtd/nand/raw/nand_base.c | 21 |
1 files changed, 2 insertions, 19 deletions
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 5698c1e6a22..4ea7f10a06f 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -4163,12 +4163,11 @@ static int nand_get_bits_per_cell(u8 cellinfo) void nand_decode_ext_id(struct nand_chip *chip) { struct mtd_info *mtd = &chip->mtd; - int extid, id_len; + int extid; /* The 3rd id byte holds MLC / multichip data */ chip->bits_per_cell = nand_get_bits_per_cell(chip->id.data[2]); /* The 4th id byte is the important one */ extid = chip->id.data[3]; - id_len = chip->id.len; /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); @@ -4184,21 +4183,6 @@ void nand_decode_ext_id(struct nand_chip *chip) /* Get buswidth information */ if (extid & 0x1) chip->options |= NAND_BUSWIDTH_16; - - /* - * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per - * 512B page. For Toshiba SLC, we decode the 5th/6th byte as - * follows: - * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm, - * 110b -> 24nm - * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC - */ - if (id_len >= 6 && chip->id.data[0] == NAND_MFR_TOSHIBA && - nand_is_slc(chip) && - (chip->id.data[5] & 0x7) == 0x6 /* 24nm */ && - !(chip->id.data[4] & 0x80) /* !BENAND */) { - mtd->oobsize = 32 * mtd->writesize >> 9; - } } EXPORT_SYMBOL_GPL(nand_decode_ext_id); @@ -4289,8 +4273,7 @@ static void nand_decode_bbm_options(struct mtd_info *mtd, * AMD/Spansion, and Macronix. All others scan only the first page. */ if ((nand_is_slc(chip) && - (maf_id == NAND_MFR_TOSHIBA || - maf_id == NAND_MFR_AMD || + (maf_id == NAND_MFR_AMD || maf_id == NAND_MFR_MACRONIX)) || (mtd->writesize == 2048 && maf_id == NAND_MFR_MICRON)) chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; |