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| author | Michal Simek <michal.simek@amd.com> | 2024-09-13 09:37:38 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2024-09-20 15:31:19 +0200 |
| commit | 6161eaf05794ab2fc1af2b0159083ab6b955e20c (patch) | |
| tree | f9c9dc7f5eaaf68ca36a9e76038745cc3e280b44 /drivers/net/aspeed_mdio.c | |
| parent | 067e0294806eb132e01f64d89a4df9a9cc857692 (diff) | |
| download | u-boot-6161eaf05794ab2fc1af2b0159083ab6b955e20c.tar.gz | |
net: gem: Remove undocumented is-internal-pcspma dt flag
Generic understanding/consideration is that phy-mode as sgmi means that the
internal PCS(Physical Coding Sublayer) should be enabled by default.
Xilinx GEM implementation allows configuration GEM (gmii mode) + PL PCS PMA
(sgmii mode, Physical Medum Attachment) but in this case phy-mode should be
setup as gmii.
The reason for this assumption is that phy-mode should be described based
on GEM configuration not based on mode coming out of PHY.
Also Linux kernel automatically setting up PCSSEL bit when phy mode is
sgmii without a need to specified additional DT propety.
All our DTSes with sgmii phy mode have this flag enabled that's why there
is no need/reason to just duplicate information.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2ecdbcc4ce692e2f8b3e7054a2abab35f6c03a69.1726213052.git.michal.simek@amd.com
Diffstat (limited to 'drivers/net/aspeed_mdio.c')
0 files changed, 0 insertions, 0 deletions