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authorwdenk <wdenk>2003-07-16 21:53:01 +0000
committerwdenk <wdenk>2003-07-16 21:53:01 +0000
commit945af8d723a29e9b6289d84250745ed0dc16fc81 (patch)
tree6798d0b717c05b01742df0c410038c702b8a1979 /drivers
parentcb4dbb7bbc271f988e14ec353a5e86d7f10e1da0 (diff)
downloadu-boot-945af8d723a29e9b6289d84250745ed0dc16fc81.tar.gz
* Add support for IceCube board (with MGT5100 and MPC5200 CPUs)U-Boot-0_4_4
* Add support for MGT5100 and MPC5200 processors
Diffstat (limited to 'drivers')
-rw-r--r--drivers/ns16550.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ns16550.c b/drivers/ns16550.c
index 9344a0a645d..b20ae4b2d51 100644
--- a/drivers/ns16550.c
+++ b/drivers/ns16550.c
@@ -17,9 +17,9 @@
void NS16550_init (NS16550_t com_port, int baud_divisor)
{
com_port->ier = 0x00;
-#ifdef CONFIG_OMAP1510
+#ifdef CONFIG_OMAP1510
com_port->mdr1 = 0x7; /* mode select reset TL16C750*/
-#endif
+#endif
com_port->lcr = LCR_BKSE | LCRVAL;
com_port->dll = baud_divisor & 0xff;
com_port->dlm = (baud_divisor >> 8) & 0xff;
OAD_VAL 0x0 #define DW_APB_CURR_VAL 0x4 #define DW_APB_CTRL 0x8 struct dw_apb_timer_priv { fdt_addr_t regs; struct reset_ctl_bulk resets; }; static u64 dw_apb_timer_get_count(struct udevice *dev) { struct dw_apb_timer_priv *priv = dev_get_priv(dev); /* * The DW APB counter counts down, but this function * requires the count to be incrementing. Invert the * result. */ return timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL)); } static int dw_apb_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct dw_apb_timer_priv *priv = dev_get_priv(dev); struct clk clk; int ret; ret = reset_get_bulk(dev, &priv->resets); if (ret) dev_warn(dev, "Can't get reset: %d\n", ret); else reset_deassert_bulk(&priv->resets); ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; uc_priv->clock_rate = clk_get_rate(&clk); clk_free(&clk); /* init timer */ writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL); writel(0xffffffff, priv->regs + DW_APB_CURR_VAL); setbits_le32(priv->regs + DW_APB_CTRL, 0x3); return 0; } static int dw_apb_timer_of_to_plat(struct udevice *dev) { struct dw_apb_timer_priv *priv = dev_get_priv(dev); priv->regs = dev_read_addr(dev); return 0; } static int dw_apb_timer_remove(struct udevice *dev) { struct dw_apb_timer_priv *priv = dev_get_priv(dev); return reset_release_bulk(&priv->resets); } static const struct timer_ops dw_apb_timer_ops = { .get_count = dw_apb_timer_get_count, }; static const struct udevice_id dw_apb_timer_ids[] = { { .compatible = "snps,dw-apb-timer" }, {} }; U_BOOT_DRIVER(dw_apb_timer) = { .name = "dw_apb_timer", .id = UCLASS_TIMER, .ops = &dw_apb_timer_ops, .probe = dw_apb_timer_probe, .of_match = dw_apb_timer_ids, .of_to_plat = dw_apb_timer_of_to_plat, .remove = dw_apb_timer_remove, .priv_auto = sizeof(struct dw_apb_timer_priv), };