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Diffstat (limited to 'board/aristainetos/aristainetos.c')
-rw-r--r--board/aristainetos/aristainetos.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index c88b9fc8c0e..9f744b30b3e 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -20,7 +20,7 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/mach-imx/video.h>
#include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
@@ -107,7 +107,7 @@ int dram_init(void)
return 0;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR},
{USDHC2_BASE_ADDR},
generated by cgit (git 2.34.1) at 2025-02-26 17:23:53 +0000
lass="hl kwb">struct drm_display_mode *adjusted_mode, int x, int y, struct drm_framebuffer *old_fb) { struct drm_device *dev = crtc->dev; struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct drm_nouveau_private *dev_priv = dev->dev_private; NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index); drm_mode_debug_printmodeline(adjusted_mode); /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); nv_crtc_mode_set_vga(crtc, adjusted_mode); /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ if (dev_priv->card_type == NV_40) NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk); nv_crtc_mode_set_regs(crtc, adjusted_mode); nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); return 0; } static void nv_crtc_save(struct drm_crtc *crtc) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; struct nv04_mode_state *state = &dev_priv->mode_reg; struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; struct nv04_mode_state *saved = &dev_priv->saved_reg; struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; if (nv_two_heads(crtc->dev)) NVSetOwner(crtc->dev, nv_crtc->index); nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); /* init some state to saved value */ state->sel_clk = saved->sel_clk & ~(0x5 << 16); crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); crtc_state->gpio_ext = crtc_saved->gpio_ext; } static void nv_crtc_restore(struct drm_crtc *crtc) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; int head = nv_crtc->index; uint8_t saved_cr21 = dev_priv->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; if (nv_two_heads(crtc->dev)) NVSetOwner(crtc->dev, head); nouveau_hw_load_state(crtc->dev, head, &dev_priv->saved_reg); nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); nv_crtc->last_dpms = NV_DPMS_CLEARED; } static void nv_crtc_prepare(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct drm_crtc_helper_funcs *funcs = crtc->helper_private; if (nv_two_heads(dev)) NVSetOwner(dev, nv_crtc->index); funcs->dpms(crtc, DRM_MODE_DPMS_OFF); NVBlankScreen(dev, nv_crtc->index, true); /* Some more preperation. */ NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); if (dev_priv->card_type == NV_40) { uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); } } static void nv_crtc_commit(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_crtc_helper_funcs *funcs = crtc->helper_private; struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nouveau_hw_load_state(dev, nv_crtc->index, &dev_priv->mode_reg); nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); #ifdef __BIG_ENDIAN /* turn on LFB swapping */ { uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); } #endif funcs->dpms(crtc, DRM_MODE_DPMS_ON); } static void nv_crtc_destroy(struct drm_crtc *crtc) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); NV_DEBUG_KMS(crtc->dev, "\n"); if (!nv_crtc) return; drm_crtc_cleanup(crtc); nouveau_bo_unmap(nv_crtc->cursor.nvbo); nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); kfree(nv_crtc); } static void nv_crtc_gamma_load(struct drm_crtc *crtc) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct drm_device *dev = nv_crtc->base.dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; int i; rgbs = (struct rgb *)dev_priv->mode_reg.crtc_reg[nv_crtc->index].DAC; for (i = 0; i < 256; i++) { rgbs[i].r = nv_crtc->lut.r[i] >> 8; rgbs[i].g = nv_crtc->lut.g[i] >> 8; rgbs[i].b = nv_crtc->lut.b[i] >> 8; } nouveau_hw_load_state_palette(dev, nv_crtc->index, &dev_priv->mode_reg); } static void nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start, uint32_t size) { int end = (start + size > 256) ? 256 : start + size, i; struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); for (i = start; i < end; i++) { nv_crtc->lut.r[i] = r[i]; nv_crtc->lut.g[i] = g[i]; nv_crtc->lut.b[i] = b[i]; } /* We need to know the depth before we upload, but it's possible to * get called before a framebuffer is bound. If this is the case, * mark the lut values as dirty by setting depth==0, and it'll be * uploaded on the first mode_set_base() */ if (!nv_crtc->base.fb) { nv_crtc->lut.depth = 0; return; } nv_crtc_gamma_load(crtc); } static int nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, struct drm_framebuffer *passed_fb, int x, int y, bool atomic) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct drm_device *dev = crtc->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index]; struct drm_framebuffer *drm_fb = nv_crtc->base.fb; struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); int arb_burst, arb_lwm; int ret; /* If atomic, we want to switch to the fb we were passed, so * now we update pointers to do that. (We don't pin; just * assume we're already pinned and update the base address.) */ if (atomic) { drm_fb = passed_fb; fb = nouveau_framebuffer(passed_fb); } else { /* If not atomic, we can go ahead and pin, and unpin the * old fb we were passed. */ ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM); if (ret) return ret; if (passed_fb) { struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb); nouveau_bo_unpin(ofb->nvbo); } } nv_crtc->fb.offset = fb->nvbo->bo.offset; if (nv_crtc->lut.depth != drm_fb->depth) { nv_crtc->lut.depth = drm_fb->depth; nv_crtc_gamma_load(crtc); } /* Update the framebuffer format. */ regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8; regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; if (crtc->fb->depth == 16) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3; regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); /* Update the framebuffer location. */ regp->fb_start = nv_crtc->fb.offset & ~3; regp->fb_start += (y * drm_fb->pitch) + (x * drm_fb->bits_per_pixel / 8); nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); /* Update the arbitration parameters. */ nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, &arb_burst, &arb_lwm); regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); if (dev_priv->card_type >= NV_20) { regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); } return 0; } static int nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, struct drm_framebuffer *old_fb) { return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); } static int nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x, int y, enum mode_set_atomic state) { struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; struct drm_device *dev = dev_priv->dev; if (state == ENTER_ATOMIC_MODE_SET) nouveau_fbcon_save_disable_accel(dev); else nouveau_fbcon_restore_accel(dev); return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); } static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, struct nouveau_bo *dst) { int width = nv_cursor_width(dev); uint32_t pixel; int i, j; for (i = 0; i < width; i++) { for (j = 0; j < width; j++) { pixel = nouveau_bo_rd32(src, i*64 + j); nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 | (pixel & 0xf80000) >> 9 | (pixel & 0xf800) >> 6 | (pixel & 0xf8) >> 3); } } } static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, struct nouveau_bo *dst) { uint32_t pixel; int alpha, i; /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha * cursors (though NPM in combination with fp dithering may not work on * nv11, from "nv" driver history) * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the * blob uses, however we get given PM cursors so we use PM mode */ for (i = 0; i < 64 * 64; i++) { pixel = nouveau_bo_rd32(src, i); /* hw gets unhappy if alpha <= rgb values. for a PM image "less * than" shouldn't happen; fix "equal to" case by adding one to * alpha channel (slightly inaccurate, but so is attempting to * get back to NPM images, due to limits of integer precision) */ alpha = pixel >> 24; if (alpha > 0 && alpha < 255) pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); #ifdef __BIG_ENDIAN { struct drm_nouveau_private *dev_priv = dev->dev_private; if (dev_priv->chipset == 0x11) { pixel = ((pixel & 0x000000ff) << 24) | ((pixel & 0x0000ff00) << 8) | ((pixel & 0x00ff0000) >> 8) | ((pixel & 0xff000000) >> 24); } } #endif nouveau_bo_wr32(dst, i, pixel); } } static int nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, uint32_t buffer_handle, uint32_t width, uint32_t height) { struct drm_nouveau_private *dev_priv = crtc->dev->dev_private; struct drm_device *dev = dev_priv->dev; struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nouveau_bo *cursor = NULL; struct drm_gem_object *gem; int ret = 0; if (width != 64 || height != 64) return -EINVAL; if (!buffer_handle) { nv_crtc->cursor.hide(nv_crtc, true); return 0; } gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); if (!gem) return -ENOENT; cursor = nouveau_gem_object(gem); ret = nouveau_bo_map(cursor); if (ret) goto out; if (dev_priv->chipset >= 0x11) nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); else nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); nouveau_bo_unmap(cursor); nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); nv_crtc->cursor.show(nv_crtc, true); out: drm_gem_object_unreference_unlocked(gem); return ret; } static int nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); nv_crtc->cursor.set_pos(nv_crtc, x, y); return 0; } static const struct drm_crtc_funcs nv04_crtc_funcs = { .save = nv_crtc_save, .restore = nv_crtc_restore, .cursor_set = nv04_crtc_cursor_set, .cursor_move = nv04_crtc_cursor_move, .gamma_set = nv_crtc_gamma_set, .set_config = drm_crtc_helper_set_config, .destroy = nv_crtc_destroy, }; static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { .dpms = nv_crtc_dpms, .prepare = nv_crtc_prepare, .commit = nv_crtc_commit, .mode_fixup = nv_crtc_mode_fixup, .mode_set = nv_crtc_mode_set, .mode_set_base = nv04_crtc_mode_set_base, .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, .load_lut = nv_crtc_gamma_load, }; int nv04_crtc_create(struct drm_device *dev, int crtc_num) { struct nouveau_crtc *nv_crtc; int ret, i; nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); if (!nv_crtc) return -ENOMEM; for (i = 0; i < 256; i++) { nv_crtc->lut.r[i] = i << 8; nv_crtc->lut.g[i] = i << 8; nv_crtc->lut.b[i] = i << 8; } nv_crtc->lut.depth = 0; nv_crtc->index = crtc_num; nv_crtc->last_dpms = NV_DPMS_CLEARED; drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, 0, 0x0000, false, true, &nv_crtc->cursor.nvbo); if (!ret) { ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); if (!ret) ret = nouveau_bo_map(nv_crtc->cursor.nvbo); if (ret) nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); } nv04_cursor_init(nv_crtc); return 0; }
generated by cgit (git 2.34.1) at 2025-02-26 17:23:53 +0000