| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | riscv: cpu: jh7110: Sort the list of imply statements | Hal Feng | 2024-12-18 | 1 | -10/+10 |
| * | dts: starfive: Switch to using upstream DT | Hal Feng | 2024-12-18 | 1 | -0/+1 |
| * | riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT | Shengyu Qu | 2023-09-05 | 1 | -0/+1 |
| * | riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE | Shengyu Qu | 2023-08-10 | 1 | -0/+1 |
| * | riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE | Minda Chen | 2023-08-10 | 1 | -0/+1 |
| * | riscv: Rename SiFive CLINT to RISC-V ALINT | Bin Meng | 2023-07-12 | 1 | -1/+1 |
| * | riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC | Yanhong Wang | 2023-04-20 | 1 | -0/+28 |
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