diff options
author | Laszlo Ersek <lersek@redhat.com> | 2018-02-01 23:40:29 +0100 |
---|---|---|
committer | Laszlo Ersek <lersek@redhat.com> | 2018-04-04 16:44:06 +0200 |
commit | c455687fd0babe03a203b38c9a884c65198d8c1d (patch) | |
tree | cfaf6d86fd83174f8851813ad787ccb41fcbfa5f /UefiCpuPkg/PiSmmCpuDxeSmm/Ia32 | |
parent | fc504fdea7fe92bfa88e15f50e64b4d76d4f75fd (diff) | |
download | edk2-c455687fd0babe03a203b38c9a884c65198d8c1d.tar.gz |
UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmiCr3" with PatchInstructionX86()
Rename the variable to "gPatchSmiCr3" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(). This
lets us remove the binary (DB) encoding of some instructions in
"SmiEntry.nasm".
Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'UefiCpuPkg/PiSmmCpuDxeSmm/Ia32')
-rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm index 0ea3c1e449..0023cb328d 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm @@ -44,7 +44,7 @@ extern ASM_PFX(CpuSmmDebugExit) global ASM_PFX(gcSmiHandlerTemplate)
global ASM_PFX(gcSmiHandlerSize)
-global ASM_PFX(gSmiCr3)
+global ASM_PFX(gPatchSmiCr3)
global ASM_PFX(gPatchSmiStack)
global ASM_PFX(gPatchSmbase)
global ASM_PFX(mXdSupported)
@@ -93,8 +93,8 @@ ASM_PFX(gPatchSmiStack): jmp ProtFlatMode
ProtFlatMode:
- DB 0xb8 ; mov eax, imm32
-ASM_PFX(gSmiCr3): DD 0
+ mov eax, strict dword 0 ; source operand will be patched
+ASM_PFX(gPatchSmiCr3):
mov cr3, eax
;
; Need to test for CR4 specific bit support
|